Commit 5d82c82f authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Update soc bounding box for dcn32/dcn321 



[Description]
New values for soc bounding box and dummy pstate.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarDillon Varone <Dillon.Varone@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
parent 44035ec2

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+3 −3
Original line number Diff line number Diff line
@@ -157,7 +157,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { 
	.dispclk_dppclk_vco_speed_mhz = 4300.0,

	.do_urgent_latency_adjustment = true,

	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,

};



void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
@@ -211,7 +211,7 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) 
	/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */

	if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {

		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;

		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38;

		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;

		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;

		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;

		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
@@ -221,7 +221,7 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) 
		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;

		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;

		clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;

		clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;

		clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;

		clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;

		clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;

		clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

+4 −4
Original line number Diff line number Diff line
@@ -126,9 +126,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { 
	.sr_enter_plus_exit_z8_time_us = 320,

	.writeback_latency_us = 12.0,

	.round_trip_ping_latency_dcfclk_cycles = 263,

	.urgent_latency_pixel_data_only_us = 9.35,

	.urgent_latency_pixel_mixed_with_vm_data_us = 9.35,

	.urgent_latency_vm_data_only_us = 9.35,

	.urgent_latency_pixel_data_only_us = 4,

	.urgent_latency_pixel_mixed_with_vm_data_us = 4,

	.urgent_latency_vm_data_only_us = 4,

	.fclk_change_latency_us = 20,

	.usr_retraining_latency_us = 2,

	.smn_latency_us = 2,
@@ -156,7 +156,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { 
	.dispclk_dppclk_vco_speed_mhz = 4300.0,

	.do_urgent_latency_adjustment = true,

	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,

};



static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)