Commit 5d4193c6 authored by Alexander Lobakin's avatar Alexander Lobakin Committed by David S. Miller
Browse files

qed: reformat several structures a bit 



Reformat a few nvm_cfg* structures (and partly qed_dev) prior to adding
new fields and definitions.

Signed-off-by: default avatarAlexander Lobakin <alobakin@marvell.com>
Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9bdca14a

drivers/net/ethernet/qlogic/qed/qed.h

+55 −54
Original line number Diff line number Diff line
@@ -302,12 +302,12 @@ struct qed_hw_info { 
	/* Resource Allocation scheme results */

	u32				resc_start[QED_MAX_RESC];

	u32				resc_num[QED_MAX_RESC];

	u32				feat_num[QED_MAX_FEATURES];



#define RESC_START(_p_hwfn, resc)	((_p_hwfn)->hw_info.resc_start[resc])

#define RESC_NUM(_p_hwfn, resc)		((_p_hwfn)->hw_info.resc_num[resc])

#define RESC_END(_p_hwfn, resc)		(RESC_START(_p_hwfn, resc) +	\

					 RESC_NUM(_p_hwfn, resc))



	u32				feat_num[QED_MAX_FEATURES];

#define FEAT_NUM(_p_hwfn, resc)		((_p_hwfn)->hw_info.feat_num[resc])



	/* Amount of traffic classes HW supports */
@@ -317,11 +317,12 @@ struct qed_hw_info { 
	 * layer driver configuration.

	 */

	u8				num_active_tc;



	u8				offload_tc;

	bool				offload_tc_set;



	bool				multi_tc_roce_en;

#define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))

#define IS_QED_MULTI_TC_ROCE(p_hwfn)	((p_hwfn)->hw_info.multi_tc_roce_en)



	u32				concrete_fid;

	u16				opaque_fid;
@@ -722,17 +723,17 @@ struct qed_dev { 
	enum qed_dev_type		type;

	/* Translate type/revision combo into the proper conditions */

#define QED_IS_BB(dev)			((dev)->type == QED_DEV_TYPE_BB)

#define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \

				 CHIP_REV_IS_B0(dev))

#define QED_IS_BB_B0(dev)		(QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))

#define QED_IS_AH(dev)			((dev)->type == QED_DEV_TYPE_AH)

#define QED_IS_K2(dev)			QED_IS_AH(dev)

#define QED_IS_E4(dev)			(QED_IS_BB(dev) || QED_IS_AH(dev))



	u16				vendor_id;



	u16				device_id;

#define QED_DEV_ID_MASK			0xff00

#define QED_DEV_ID_MASK_BB		0x1600

#define QED_DEV_ID_MASK_AH		0x8000

#define QED_IS_E4(dev)  (QED_IS_BB(dev) || QED_IS_AH(dev))



	u16				chip_num;

#define CHIP_NUM_MASK			0xffff

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+176 −169
Original line number Diff line number Diff line
@@ -12535,16 +12535,16 @@ struct public_drv_mb { 
#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET			0

#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK			0x00000003

#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET			2

#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK		0x000000FC

#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK			0x000000fc

#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET		8

#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK	0x0000FF00

#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK		0x0000ff00

#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET			16

#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK		0xFFFF0000

#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK			0xffff0000



	/* Resource Allocation params - Driver version support */

#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000

#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK		0xffff0000

#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT		16

#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF

#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK		0x0000ffff

#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0



#define DRV_MB_PARAM_BIST_REGISTER_TEST				1
@@ -12558,11 +12558,11 @@ struct public_drv_mb { 
#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER			3



#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT			0

#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK	0x000000FF

#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK			0x000000ff

#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT		8

#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK		0x0000FF00

#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK			0x0000ff00



#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK		0x0000FFFF

#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK			0x0000ffff

#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET		0

#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE			0x00000002

#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL		0x00000004
@@ -12570,17 +12570,17 @@ struct public_drv_mb { 


/* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */

#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET		0

#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK		0xFF

#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK			0xff



/* Driver attributes params */

#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET			0

#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK			0x00FFFFFF

#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK				0x00ffffff

#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET			24

#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK			0xFF000000

#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK				0xff000000



#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET			0

#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT			0

#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK		0x0000FFFF

#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK			0x0000ffff

#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT			16

#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK			0x00010000

#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT			17
@@ -12652,10 +12652,10 @@ struct public_drv_mb { 
#define FW_MB_PARAM_GET_PF_RDMA_BOTH				0x3



	/* Get MFW feature support response */

#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ		0x00000001

#define FW_MB_PARAM_FEATURE_SUPPORT_EEE			0x00000002

#define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL		0x00000020

#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK		0x00010000

#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ			BIT(0)

#define FW_MB_PARAM_FEATURE_SUPPORT_EEE				BIT(1)

#define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL			BIT(5)

#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK			BIT(16)



#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR			BIT(0)
@@ -12976,14 +12976,15 @@ enum tlvs { 


struct nvm_cfg_mac_address {

	u32							mac_addr_hi;

#define NVM_CFG_MAC_ADDRESS_HI_MASK	0x0000FFFF

#define NVM_CFG_MAC_ADDRESS_HI_MASK				0x0000ffff

#define NVM_CFG_MAC_ADDRESS_HI_OFFSET				0



	u32							mac_addr_lo;

};



struct nvm_cfg1_glob {

	u32							generic_cont0;

#define NVM_CFG1_GLOB_MF_MODE_MASK		0x00000FF0

#define NVM_CFG1_GLOB_MF_MODE_MASK				0x00000ff0

#define NVM_CFG1_GLOB_MF_MODE_OFFSET				4

#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED			0x0

#define NVM_CFG1_GLOB_MF_MODE_DEFAULT				0x1
@@ -12993,13 +12994,15 @@ struct nvm_cfg1_glob { 
#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0				0x5

#define NVM_CFG1_GLOB_MF_MODE_BD				0x6

#define NVM_CFG1_GLOB_MF_MODE_UFP				0x7



	u32							engineering_change[3];

	u32							manufacturing_id;

	u32							serial_number[4];

	u32							pcie_cfg;

	u32							mgmt_traffic;



	u32							core_cfg;

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK		0x000000FF

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK			0x000000ff

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET			0

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G		0x0

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G			0x1
@@ -13007,11 +13010,11 @@ struct nvm_cfg1_glob { 
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F			0x3

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E		0x4

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G		0x5

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G		0xB

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G		0xC

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G		0xD

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G		0xE

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G		0xF

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G			0xb

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G			0xc

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G			0xd

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G			0xe

#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G			0xf



	u32							e_lane_cfg1;

	u32							e_lane_cfg2;
@@ -13032,24 +13035,28 @@ struct nvm_cfg1_glob { 
	u32							manufacture_time;

	u32							led_global_settings;

	u32							generic_cont1;



	u32							mbi_version;

#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK		0x000000FF

#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK			0x000000ff

#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET			0

#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK		0x0000FF00

#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK			0x0000ff00

#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET			8

#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK		0x00FF0000

#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK			0x00ff0000

#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET			16



	u32							mbi_date;

	u32							misc_sig;



	u32							device_capabilities;

#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET		0x1

#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE			0x2

#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI			0x4

#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE			0x8



	u32							power_dissipated;

	u32							power_consumed;

	u32							efi_version;

	u32 multi_network_modes_capability;

	u32							multi_net_modes_cap;

	u32							reserved[41];

};

drivers/net/ethernet/qlogic/qed/qed_mcp.h

+6 −6
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 


struct qed_mcp_link_speed_params {

	bool					autoneg;

	u32     advertised_speeds;      /* bitmask of DRV_SPEED_CAPABILITY */

	u32					advertised_speeds;

	u32					forced_speed;	   /* In Mb/s */

};