Commit 5d1f3fe7 authored by Maxime Chevallier's avatar Maxime Chevallier Committed by David S. Miller
Browse files

net: stmmac: dwmac-sogfpga: use the lynx pcs driver 



dwmac_socfpga re-implements support for the TSE PCS, which is identical
to the already existing TSE PCS, which in turn is the same as the Lynx
PCS. Drop the existing TSE re-implemenation and use the Lynx PCS
instead, relying on the regmap-mdio driver to translate MDIO accesses
into mmio accesses.

Add a lynx_pcs reference in the stmmac's internal structure, and use
.mac_select_pcs() to return the relevant PCS to be used.

Signed-off-by: default avatarMaxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: default avatarSimon Horman <simon.horman@corigine.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 196eec40

drivers/net/ethernet/stmicro/stmmac/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -158,6 +158,9 @@ config DWMAC_SOCFPGA 
	default ARCH_INTEL_SOCFPGA

	depends on OF && (ARCH_INTEL_SOCFPGA || COMPILE_TEST)

	select MFD_SYSCON

	select MDIO_REGMAP

	select REGMAP_MMIO

	select PCS_LYNX

	help

	  Support for ethernet controller on Altera SOCFPGA

drivers/net/ethernet/stmicro/stmmac/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o 
obj-$(CONFIG_DWMAC_TEGRA)	+= dwmac-tegra.o

obj-$(CONFIG_DWMAC_VISCONTI)	+= dwmac-visconti.o

stmmac-platform-objs:= stmmac_platform.o

dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o

dwmac-altr-socfpga-objs := dwmac-socfpga.o



obj-$(CONFIG_STMMAC_PCI)	+= stmmac-pci.o

obj-$(CONFIG_DWMAC_INTEL)	+= dwmac-intel.o

drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c

deleted100644 → 0
+0 −257
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright Altera Corporation (C) 2016. All rights reserved.

 *

 * Author: Tien Hock Loh <thloh@altera.com>

 */



#include <linux/mfd/syscon.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_net.h>

#include <linux/phy.h>

#include <linux/regmap.h>

#include <linux/reset.h>

#include <linux/stmmac.h>



#include "stmmac.h"

#include "stmmac_platform.h"

#include "altr_tse_pcs.h"



#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0

#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		BIT(1)

#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		BIT(2)

#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH		2

#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			GENMASK(1, 0)



#define TSE_PCS_CONTROL_AN_EN_MASK			BIT(12)

#define TSE_PCS_CONTROL_REG				0x00

#define TSE_PCS_CONTROL_RESTART_AN_MASK			BIT(9)

#define TSE_PCS_CTRL_AUTONEG_SGMII			0x1140

#define TSE_PCS_IF_MODE_REG				0x28

#define TSE_PCS_LINK_TIMER_0_REG			0x24

#define TSE_PCS_LINK_TIMER_1_REG			0x26

#define TSE_PCS_SIZE					0x40

#define TSE_PCS_STATUS_AN_COMPLETED_MASK		BIT(5)

#define TSE_PCS_STATUS_LINK_MASK			0x0004

#define TSE_PCS_STATUS_REG				0x02

#define TSE_PCS_SGMII_SPEED_1000			BIT(3)

#define TSE_PCS_SGMII_SPEED_100				BIT(2)

#define TSE_PCS_SGMII_SPEED_10				0x0

#define TSE_PCS_SW_RST_MASK				0x8000

#define TSE_PCS_PARTNER_ABILITY_REG			0x0A

#define TSE_PCS_PARTNER_DUPLEX_FULL			0x1000

#define TSE_PCS_PARTNER_DUPLEX_HALF			0x0000

#define TSE_PCS_PARTNER_DUPLEX_MASK			0x1000

#define TSE_PCS_PARTNER_SPEED_MASK			GENMASK(11, 10)

#define TSE_PCS_PARTNER_SPEED_1000			BIT(11)

#define TSE_PCS_PARTNER_SPEED_100			BIT(10)

#define TSE_PCS_PARTNER_SPEED_10			0x0000

#define TSE_PCS_PARTNER_SPEED_1000			BIT(11)

#define TSE_PCS_PARTNER_SPEED_100			BIT(10)

#define TSE_PCS_PARTNER_SPEED_10			0x0000

#define TSE_PCS_SGMII_SPEED_MASK			GENMASK(3, 2)

#define TSE_PCS_SGMII_LINK_TIMER_0			0x0D40

#define TSE_PCS_SGMII_LINK_TIMER_1			0x0003

#define TSE_PCS_SW_RESET_TIMEOUT			100

#define TSE_PCS_USE_SGMII_AN_MASK			BIT(1)

#define TSE_PCS_USE_SGMII_ENA				BIT(0)

#define TSE_PCS_IF_USE_SGMII				0x03



#define AUTONEGO_LINK_TIMER				20



static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs)

{

	int counter = 0;

	u16 val;



	val = readw(base + TSE_PCS_CONTROL_REG);

	val |= TSE_PCS_SW_RST_MASK;

	writew(val, base + TSE_PCS_CONTROL_REG);



	while (counter < TSE_PCS_SW_RESET_TIMEOUT) {

		val = readw(base + TSE_PCS_CONTROL_REG);

		val &= TSE_PCS_SW_RST_MASK;

		if (val == 0)

			break;

		counter++;

		udelay(1);

	}

	if (counter >= TSE_PCS_SW_RESET_TIMEOUT) {

		dev_err(pcs->dev, "PCS could not get out of sw reset\n");

		return -ETIMEDOUT;

	}



	return 0;

}



int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs)

{

	int ret = 0;



	writew(TSE_PCS_IF_USE_SGMII, base + TSE_PCS_IF_MODE_REG);



	writew(TSE_PCS_CTRL_AUTONEG_SGMII, base + TSE_PCS_CONTROL_REG);



	writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG);

	writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG);



	ret = tse_pcs_reset(base, pcs);

	if (ret == 0)

		writew(SGMII_ADAPTER_ENABLE,

		       pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);



	return ret;

}



static void pcs_link_timer_callback(struct tse_pcs *pcs)

{

	u16 val = 0;

	void __iomem *tse_pcs_base = pcs->tse_pcs_base;

	void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;



	val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);

	val &= TSE_PCS_STATUS_LINK_MASK;



	if (val != 0) {

		dev_dbg(pcs->dev, "Adapter: Link is established\n");

		writew(SGMII_ADAPTER_ENABLE,

		       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);

	} else {

		mod_timer(&pcs->aneg_link_timer, jiffies +

			  msecs_to_jiffies(AUTONEGO_LINK_TIMER));

	}

}



static void auto_nego_timer_callback(struct tse_pcs *pcs)

{

	u16 val = 0;

	u16 speed = 0;

	u16 duplex = 0;

	void __iomem *tse_pcs_base = pcs->tse_pcs_base;

	void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;



	val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);

	val &= TSE_PCS_STATUS_AN_COMPLETED_MASK;



	if (val != 0) {

		dev_dbg(pcs->dev, "Adapter: Auto Negotiation is completed\n");

		val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG);

		speed = val & TSE_PCS_PARTNER_SPEED_MASK;

		duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK;



		if (speed == TSE_PCS_PARTNER_SPEED_10 &&

		    duplex == TSE_PCS_PARTNER_DUPLEX_FULL)

			dev_dbg(pcs->dev,

				"Adapter: Link Partner is Up - 10/Full\n");

		else if (speed == TSE_PCS_PARTNER_SPEED_100 &&

			 duplex == TSE_PCS_PARTNER_DUPLEX_FULL)

			dev_dbg(pcs->dev,

				"Adapter: Link Partner is Up - 100/Full\n");

		else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&

			 duplex == TSE_PCS_PARTNER_DUPLEX_FULL)

			dev_dbg(pcs->dev,

				"Adapter: Link Partner is Up - 1000/Full\n");

		else if (speed == TSE_PCS_PARTNER_SPEED_10 &&

			 duplex == TSE_PCS_PARTNER_DUPLEX_HALF)

			dev_err(pcs->dev,

				"Adapter does not support Half Duplex\n");

		else if (speed == TSE_PCS_PARTNER_SPEED_100 &&

			 duplex == TSE_PCS_PARTNER_DUPLEX_HALF)

			dev_err(pcs->dev,

				"Adapter does not support Half Duplex\n");

		else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&

			 duplex == TSE_PCS_PARTNER_DUPLEX_HALF)

			dev_err(pcs->dev,

				"Adapter does not support Half Duplex\n");

		else

			dev_err(pcs->dev,

				"Adapter: Invalid Partner Speed and Duplex\n");



		if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL &&

		    (speed == TSE_PCS_PARTNER_SPEED_10 ||

		     speed == TSE_PCS_PARTNER_SPEED_100 ||

		     speed == TSE_PCS_PARTNER_SPEED_1000))

			writew(SGMII_ADAPTER_ENABLE,

			       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);

	} else {

		val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);

		val |= TSE_PCS_CONTROL_RESTART_AN_MASK;

		writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);



		tse_pcs_reset(tse_pcs_base, pcs);

		mod_timer(&pcs->aneg_link_timer, jiffies +

			  msecs_to_jiffies(AUTONEGO_LINK_TIMER));

	}

}



static void aneg_link_timer_callback(struct timer_list *t)

{

	struct tse_pcs *pcs = from_timer(pcs, t, aneg_link_timer);



	if (pcs->autoneg == AUTONEG_ENABLE)

		auto_nego_timer_callback(pcs);

	else if (pcs->autoneg == AUTONEG_DISABLE)

		pcs_link_timer_callback(pcs);

}



void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,

			   unsigned int speed)

{

	void __iomem *tse_pcs_base = pcs->tse_pcs_base;

	u32 val;



	pcs->autoneg = phy_dev->autoneg;



	if (phy_dev->autoneg == AUTONEG_ENABLE) {

		val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);

		val |= TSE_PCS_CONTROL_AN_EN_MASK;

		writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);



		val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);

		val |= TSE_PCS_USE_SGMII_AN_MASK;

		writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);



		val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);

		val |= TSE_PCS_CONTROL_RESTART_AN_MASK;



		tse_pcs_reset(tse_pcs_base, pcs);



		timer_setup(&pcs->aneg_link_timer, aneg_link_timer_callback,

			    0);

		mod_timer(&pcs->aneg_link_timer, jiffies +

			  msecs_to_jiffies(AUTONEGO_LINK_TIMER));

	} else if (phy_dev->autoneg == AUTONEG_DISABLE) {

		val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);

		val &= ~TSE_PCS_CONTROL_AN_EN_MASK;

		writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);



		val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);

		val &= ~TSE_PCS_USE_SGMII_AN_MASK;

		writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);



		val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);

		val &= ~TSE_PCS_SGMII_SPEED_MASK;



		switch (speed) {

		case 1000:

			val |= TSE_PCS_SGMII_SPEED_1000;

			break;

		case 100:

			val |= TSE_PCS_SGMII_SPEED_100;

			break;

		case 10:

			val |= TSE_PCS_SGMII_SPEED_10;

			break;

		default:

			return;

		}

		writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);



		tse_pcs_reset(tse_pcs_base, pcs);



		timer_setup(&pcs->aneg_link_timer, aneg_link_timer_callback,

			    0);

		mod_timer(&pcs->aneg_link_timer, jiffies +

			  msecs_to_jiffies(AUTONEGO_LINK_TIMER));

	}

}

drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.h

deleted100644 → 0
+0 −29
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright Altera Corporation (C) 2016. All rights reserved.

 *

 * Author: Tien Hock Loh <thloh@altera.com>

 */



#ifndef __TSE_PCS_H__

#define __TSE_PCS_H__



#include <linux/phy.h>

#include <linux/timer.h>



#define SGMII_ADAPTER_CTRL_REG		0x00

#define SGMII_ADAPTER_ENABLE		0x0000

#define SGMII_ADAPTER_DISABLE		0x0001



struct tse_pcs {

	struct device *dev;

	void __iomem *tse_pcs_base;

	void __iomem *sgmii_adapter_base;

	struct timer_list aneg_link_timer;

	int autoneg;

};



int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs);

void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,

			   unsigned int speed);



#endif /* __TSE_PCS_H__ */

drivers/net/ethernet/stmicro/stmmac/common.h

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <linux/stmmac.h>

#include <linux/phy.h>

#include <linux/pcs/pcs-xpcs.h>

#include <linux/pcs-lynx.h>

#include <linux/module.h>

#if IS_ENABLED(CONFIG_VLAN_8021Q)

#define STMMAC_VLAN_TAG_USED
@@ -519,6 +520,7 @@ struct mac_device_info { 
	const struct stmmac_tc_ops *tc;

	const struct stmmac_mmc_ops *mmc;

	struct dw_xpcs *xpcs;

	struct phylink_pcs *lynx_pcs; /* Lynx external PCS */

	struct mii_regs mii;	/* MII register Addresses */

	struct mac_link link;

	void __iomem *pcsr;     /* vpointer to device CSRs */