Commit 5cfad4f4 authored by Oliver Stäbler's avatar Oliver Stäbler Committed by Shawn Guo
Browse files

arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0 



Fix address of the pad control register
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2.  This seems
to be a typo but it leads to an exception when pinctrl is applied due to
wrong memory address access.

Signed-off-by: default avatarOliver Stäbler <oliver.staebler@bytesatwork.ch>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Fixes: c1c9d413 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm")
Fixes: 748f908c ("arm64: add basic DTS for i.MX8MQ")
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e4817a1b

arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h

+1 −1
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ 
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0

#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0

#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0

#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0

#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x310 0x000 0x5 0x0

#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0

#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0

#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0

arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h

+1 −1
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ 
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0

#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0

#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0

#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0

#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x310 0x000 0x5 0x0

#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0

#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0

#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0