Unverified Commit 5cdd5ec1 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-fixes-6.4-2' of... 

Merge tag 'imx-fixes-6.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 6.4, round 2:

- Fix SPI CS pinmux for the final production version of imx8mn-beacon
  board.
- Fix GPIOs for USDHC2 CD and WP signals on imx8qm-mek board.
- Assign default clock rate for i.MX8 LPUARTs to fix UART failure.

* tag 'imx-fixes-6.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8mn-beacon: Fix SPI CS pinmux
  arm64: dts: imx8-ss-dma: assign default clock rate for lpuarts
  arm64: dts: imx8qm-mek: correct GPIOs for USDHC2 CD and WP signals

Link: https://lore.kernel.org/r/20230607141312.GU4199@dragon


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents abd649fd 9bf2e534

arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -90,6 +90,8 @@ dma_subsys: bus@5a000000 { 
		clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,

			 <&uart0_lpcg IMX_LPCG_CLK_0>;

		clock-names = "ipg", "baud";

		assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <80000000>;

		power-domains = <&pd IMX_SC_R_UART_0>;

		status = "disabled";

	};
@@ -100,6 +102,8 @@ dma_subsys: bus@5a000000 { 
		clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,

			 <&uart1_lpcg IMX_LPCG_CLK_0>;

		clock-names = "ipg", "baud";

		assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <80000000>;

		power-domains = <&pd IMX_SC_R_UART_1>;

		status = "disabled";

	};
@@ -110,6 +114,8 @@ dma_subsys: bus@5a000000 { 
		clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,

			 <&uart2_lpcg IMX_LPCG_CLK_0>;

		clock-names = "ipg", "baud";

		assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <80000000>;

		power-domains = <&pd IMX_SC_R_UART_2>;

		status = "disabled";

	};
@@ -120,6 +126,8 @@ dma_subsys: bus@5a000000 { 
		clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,

			 <&uart3_lpcg IMX_LPCG_CLK_0>;

		clock-names = "ipg", "baud";

		assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <80000000>;

		power-domains = <&pd IMX_SC_R_UART_3>;

		status = "disabled";

	};

arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ 
&ecspi2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_espi2>;

	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;

	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;

	status = "okay";



	eeprom@0 {
@@ -202,7 +202,7 @@ 
			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82

			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82

			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82

			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41

			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x41

		>;

	};

arch/arm64/boot/dts/freescale/imx8qm-mek.dts

+2 −2
Original line number Diff line number Diff line
@@ -82,8 +82,8 @@ 
	pinctrl-0 = <&pinctrl_usdhc2>;

	bus-width = <4>;

	vmmc-supply = <&reg_usdhc2_vmmc>;

	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;

	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;

	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;

	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;

	status = "okay";

};