Commit 5cd69651 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by Michael Ellerman
Browse files

powerpc/powernv/pci: Set the IRQ chip data for P8/CXL devices 



Before MSI domains, the default IRQ chip of PHB3 MSIs was patched by
pnv_set_msi_irq_chip() with the custom EOI handler pnv_ioda2_msi_eoi()
and the owning PHB was deduced from the 'ioda.irq_chip' field. This
path has been deprecated by the MSI domains but it is still in use by
the P8 CAPI 'cxl' driver.

Rewriting this driver to support MSI would be a waste of time.
Nevertheless, we can still remove the IRQ chip patch and set the IRQ
chip data instead. This is cleaner.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210701132750.1475580-29-clg@kaod.org
parent c80198a2

arch/powerpc/platforms/powernv/pci-ioda.c

+8 −3
Original line number Diff line number Diff line
@@ -1971,19 +1971,23 @@ int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) 
	return opal_pci_msi_eoi(phb->opal_id, hw_irq);

}



/*

 * The IRQ data is mapped in the XICS domain, with OPAL HW IRQ numbers

 */

static void pnv_ioda2_msi_eoi(struct irq_data *d)

{

	int64_t rc;

	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);

	struct irq_chip *chip = irq_data_get_irq_chip(d);

	struct pci_controller *hose = irq_data_get_irq_chip_data(d);

	struct pnv_phb *phb = hose->private_data;



	rc = pnv_opal_pci_msi_eoi(chip, hw_irq);

	rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);

	WARN_ON_ONCE(rc);



	icp_native_eoi(d);

}





/* P8/CXL only */

void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)

{

	struct irq_data *idata;
@@ -2005,6 +2009,7 @@ void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) 
		phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;

	}

	irq_set_chip(virq, &phb->ioda.irq_chip);

	irq_set_chip_data(virq, phb->hose);

}



static struct irq_chip pnv_pci_msi_irq_chip;