Commit 5c844d57 authored by Rasmus Villemoes's avatar Rasmus Villemoes Committed by Jakub Kicinski
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net: dsa: microchip: fix writes to phy registers >= 0x10 



According to the errata sheets for ksz9477 and ksz9567, writes to the
PHY registers 0x10-0x1f (i.e. those located at addresses 0xN120 to
0xN13f) must be done as a 32 bit write to the 4-byte aligned address
containing the register, hence requires a RMW in order not to change
the adjacent PHY register.

Signed-off-by: default avatarRasmus Villemoes <linux@rasmusvillemoes.dk>
Reviewed-by: default avatarSimon Horman <simon.horman@corigine.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230620113855.733526-4-linux@rasmusvillemoes.dk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent ece28ecb

drivers/net/dsa/microchip/ksz9477.c

+17 −1
Original line number Diff line number Diff line
@@ -329,11 +329,27 @@ int ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 


int ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)

{

	u32 mask, val32;



	/* No real PHY after this. */

	if (!dev->info->internal_phy[addr])

		return 0;



	if (reg < 0x10)

		return ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);



	/* Errata: When using SPI, I2C, or in-band register access,

	 * writes to certain PHY registers should be performed as

	 * 32-bit writes instead of 16-bit writes.

	 */

	val32 = val;

	mask = 0xffff;

	if ((reg & 1) == 0) {

		val32 <<= 16;

		mask <<= 16;

	}

	reg &= ~1;

	return ksz_prmw32(dev, addr, 0x100 + (reg << 1), mask, val32);

}



void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member)