Unverified Commit 5c785014 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'qcom-drivers-for-5.15' of... 

Merge tag 'qcom-drivers-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.15

This fixes the "shared memory state machine" (SMSM) interrupt logic to
avoid missing transitions happening while the interrupts are masked.

SM6115 support is added to smd-rpm and rpmpd.

The Qualcomm SCM firmware driver is once again made possible to compile
and load as a kernel module.

An out-of-bounds error related to the cooling devices of the AOSS driver
is corrected. The binding is converted to YAML and a generic compatible
is introduced to reduce the driver churn.

The GENI wrapper gains a helper function used in I2C and SPI for
switching the serial engine hardware to use the wrapper's DMA-engine.

Lastly it contains a number of cleanups and smaller fixes for rpmhpd,
socinfo, CPR, mdt_loader and the GENI DT binding.

* tag 'qcom-drivers-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: smsm: Fix missed interrupts if state changes while masked
  soc: qcom: smsm: Implement support for get_irqchip_state
  soc: qcom: mdt_loader: be more informative on errors
  dt-bindings: qcom: geni-se: document iommus
  soc: qcom: smd-rpm: Add SM6115 compatible
  soc: qcom: geni: Add support for gpi dma
  soc: qcom: geni: move GENI_IF_DISABLE_RO to common header
  PM: AVS: qcom-cpr: Use nvmem_cell_read_variable_le_u32()
  drivers: soc: qcom: rpmpd: Add SM6115 RPM Power Domains
  dt-bindings: power: rpmpd: Add SM6115 to rpmpd binding
  dt-bindings: soc: qcom: smd-rpm: Add SM6115 compatible
  soc: qcom: aoss: Fix the out of bound usage of cooling_devs
  firmware: qcom_scm: Allow qcom_scm driver to be loadable as a permenent module
  soc: qcom: socinfo: Don't print anything if nothing found
  soc: qcom: rpmhpd: Use corner in power_off
  soc: qcom: aoss: Add generic compatible
  dt-bindings: soc: qcom: aoss: Convert to YAML
  dt-bindings: soc: qcom: aoss: Add SC8180X and generic compatible
  firmware: qcom_scm: remove a duplicative condition
  firmware: qcom_scm: Mark string array const

Link: https://lore.kernel.org/r/20210816214840.581244-1-bjorn.andersson@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 63db5acb e3d45719

Documentation/devicetree/bindings/power/qcom,rpmpd.yaml

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@@ -30,6 +30,7 @@ properties: 
      - qcom,sc8180x-rpmhpd

      - qcom,sdm845-rpmhpd

      - qcom,sdx55-rpmhpd

      - qcom,sm6115-rpmpd

      - qcom,sm8150-rpmhpd

      - qcom,sm8250-rpmhpd

      - qcom,sm8350-rpmhpd

Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt

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Qualcomm Always-On Subsystem side channel binding



This binding describes the hardware component responsible for side channel

requests to the always-on subsystem (AOSS), used for certain power management

requests that is not handled by the standard RPMh interface. Each client in the

SoC has it's own block of message RAM and IRQ for communication with the AOSS.

The protocol used to communicate in the message RAM is known as Qualcomm

Messaging Protocol (QMP)



The AOSS side channel exposes control over a set of resources, used to control

a set of debug related clocks and to affect the low power state of resources

related to the secondary subsystems. These resources are exposed as a set of

power-domains.



- compatible:

	Usage: required

	Value type: <string>

	Definition: must be one of:

		    "qcom,sc7180-aoss-qmp"

		    "qcom,sc7280-aoss-qmp"

		    "qcom,sdm845-aoss-qmp"

		    "qcom,sm8150-aoss-qmp"

		    "qcom,sm8250-aoss-qmp"

		    "qcom,sm8350-aoss-qmp"



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: the base address and size of the message RAM for this

		    client's communication with the AOSS



- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: should specify the AOSS message IRQ for this client



- mboxes:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: reference to the mailbox representing the outgoing doorbell

		    in APCS for this client, as described in mailbox/mailbox.txt



- #clock-cells:

	Usage: optional

	Value type: <u32>

	Definition: must be 0

		    The single clock represents the QDSS clock.



- #power-domain-cells:

	Usage: optional

	Value type: <u32>

	Definition: must be 1

		    The provided power-domains are:

		    CDSP state (0), LPASS state (1), modem state (2), SLPI

		    state (3), SPSS state (4) and Venus state (5).



= SUBNODES

The AOSS side channel also provides the controls for three cooling devices,

these are expressed as subnodes of the QMP node. The name of the node is used

to identify the resource and must therefor be "cx", "mx" or "ebi".



- #cooling-cells:

	Usage: optional

	Value type: <u32>

	Definition: must be 2



= EXAMPLE



The following example represents the AOSS side-channel message RAM and the

mechanism exposing the power-domains, as found in SDM845.



  aoss_qmp: qmp@c300000 {

	  compatible = "qcom,sdm845-aoss-qmp";

	  reg = <0x0c300000 0x100000>;

	  interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

	  mboxes = <&apss_shared 0>;



	  #power-domain-cells = <1>;



	  cx_cdev: cx {

		#cooling-cells = <2>;

	  };



	  mx_cdev: mx {

		#cooling-cells = <2>;

	  };

  };

Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Always-On Subsystem side channel binding



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



description:

  This binding describes the hardware component responsible for side channel

  requests to the always-on subsystem (AOSS), used for certain power management

  requests that is not handled by the standard RPMh interface. Each client in the

  SoC has it's own block of message RAM and IRQ for communication with the AOSS.

  The protocol used to communicate in the message RAM is known as Qualcomm

  Messaging Protocol (QMP)



  The AOSS side channel exposes control over a set of resources, used to control

  a set of debug related clocks and to affect the low power state of resources

  related to the secondary subsystems. These resources are exposed as a set of

  power-domains.



properties:

  compatible:

    items:

      - enum:

          - qcom,sc7180-aoss-qmp

          - qcom,sc7280-aoss-qmp

          - qcom,sc8180x-aoss-qmp

          - qcom,sdm845-aoss-qmp

          - qcom,sm8150-aoss-qmp

          - qcom,sm8250-aoss-qmp

          - qcom,sm8350-aoss-qmp

      - const: qcom,aoss-qmp



  reg:

    maxItems: 1

    description:

      The base address and size of the message RAM for this client's

      communication with the AOSS



  interrupts:

    maxItems: 1

    description:

      Should specify the AOSS message IRQ for this client



  mboxes:

    maxItems: 1

    description:

      Reference to the mailbox representing the outgoing doorbell in APCS for

      this client, as described in mailbox/mailbox.txt



  "#clock-cells":

    const: 0

    description:

      The single clock represents the QDSS clock.



  "#power-domain-cells":

    const: 1

    description: |

        The provided power-domains are:

        CDSP state (0), LPASS state (1), modem state (2), SLPI

        state (3), SPSS state (4) and Venus state (5).



required:

  - compatible

  - reg

  - interrupts

  - mboxes

  - "#clock-cells"



additionalProperties: false



patternProperties:

  "^(cx|mx|ebi)$":

    type: object

    description:

      The AOSS side channel also provides the controls for three cooling devices,

      these are expressed as subnodes of the QMP node. The name of the node is

      used to identify the resource and must therefor be "cx", "mx" or "ebi".



    properties:

      "#cooling-cells":

        const: 2



    required:

      - "#cooling-cells"



    additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    aoss_qmp: qmp@c300000 {

      compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";

      reg = <0x0c300000 0x100000>;

      interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

      mboxes = <&apss_shared 0>;



      #clock-cells = <0>;

      #power-domain-cells = <1>;



      cx_cdev: cx {

        #cooling-cells = <2>;

      };



      mx_cdev: mx {

        #cooling-cells = <2>;

      };

    };

...

Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml

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@@ -51,6 +51,9 @@ properties: 
  interconnect-names:

    const: qup-core



  iommus:

    maxItems: 1



required:

  - compatible

  - reg

Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml

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@@ -39,6 +39,7 @@ properties: 
      - qcom,rpm-msm8996

      - qcom,rpm-msm8998

      - qcom,rpm-sdm660

      - qcom,rpm-sm6115

      - qcom,rpm-sm6125

      - qcom,rpm-qcs404