Commit 5c6f3a36 authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
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dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings 



The GPUCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1577428714-17766-2-git-send-email-tdas@codeaurora.org


Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent fbefb7cc

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

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Qualcomm Graphics Clock & Reset Controller Binding

--------------------------------------------------



Required properties :

- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"

- reg : shall contain base register location and length

- #clock-cells : from common clock binding, shall contain 1

- #reset-cells : from common reset binding, shall contain 1

- #power-domain-cells : from generic power domain binding, shall contain 1

- clocks : shall contain the XO clock

	   shall contain the gpll0 out main clock (msm8998)

- clock-names : shall be "xo"

		shall be "gpll0" (msm8998)



Example:

	gpucc: clock-controller@5090000 {

		compatible = "qcom,sdm845-gpucc";

		reg = <0x5090000 0x9000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		#power-domain-cells = <1>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "xo";

	};

Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Graphics Clock & Reset Controller Binding



maintainers:

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm grpahics clock control module which supports the clocks, resets and

  power domains.



properties:

  compatible:

    enum:

      - qcom,msm8998-gpucc

      - qcom,sdm845-gpucc



  clocks:

    minItems: 1

    maxItems: 3

    items:

      - description: Board XO source

      - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)

      - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)



  clock-names:

    minItems: 1

    maxItems: 3

    items:

      - const: xo

      - const: gpll0_main

      - const: gpll0_div



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



examples:

  # Example of GPUCC with clock node properties for SDM845:

  - |

    clock-controller@5090000 {

      compatible = "qcom,sdm845-gpucc";

      reg = <0x5090000 0x9000>;

      clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;

      clock-names = "xo", "gpll0_main", "gpll0_div";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

     };

...