Commit 5c640bec authored by Serge Semin's avatar Serge Semin Committed by Damien Le Moal
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dt-bindings: ata: ahci: Add DWC AHCI SATA controller DT schema 



Synopsys AHCI SATA controller is mainly compatible with the generic AHCI
SATA controller except a few peculiarities and the platform environment
requirements. In particular it can have at least two reference clocks to
feed up its AHB/AXI interface and SATA PHYs domain and at least one reset
control for the application clock domain. In addition to that the DMA
interface of each port can be tuned up to work with the predefined maximum
data chunk size. Note unlike generic AHCI controller DWC AHCI can't have
more than 8 ports. All of that is reflected in the new DWC AHCI SATA
device DT binding.

Note the DWC AHCI SATA controller DT-schema has been created in a way so
to be reused for the vendor-specific DT-schemas (see for example the
"snps,dwc-ahci" compatible string binding). One of which we are about to
introduce.

Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDamien Le Moal <damien.lemoal@opensource.wdc.com>
parent 18ee7c49

Documentation/devicetree/bindings/ata/ahci-platform.yaml

+0 −8
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ select: 
          - marvell,armada-3700-ahci

          - marvell,armada-8k-ahci

          - marvell,berlin2q-ahci

          - snps,dwc-ahci

          - snps,spear-ahci

  required:

    - compatible
@@ -48,17 +46,11 @@ properties: 
              - marvell,berlin2-ahci

              - marvell,berlin2q-ahci

          - const: generic-ahci

      - items:

          - enum:

              - rockchip,rk3568-dwc-ahci

          - const: snps,dwc-ahci

      - enum:

          - cavium,octeon-7130-ahci

          - hisilicon,hisi-ahci

          - ibm,476gtr-ahci

          - marvell,armada-3700-ahci

          - snps,dwc-ahci

          - snps,spear-ahci



  reg:

    minItems: 1

Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml

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+102 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Synopsys DWC AHCI SATA controller properties



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description:

  This document defines device tree schema for the generic Synopsys DWC

  AHCI controller properties.



select: false



allOf:

  - $ref: ahci-common.yaml#



properties:

  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    description:

      Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,

      PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)

      clock, etc.

    minItems: 1

    maxItems: 4



  clock-names:

    minItems: 1

    maxItems: 4

    items:

      oneOf:

        - description: Application APB/AHB/AXI BIU clock

          enum:

            - pclk

            - aclk

            - hclk

            - sata

        - description: Power Module keep-alive clock

          const: pmalive

        - description: RxOOB detection clock

          const: rxoob

        - description: SATA Ports reference clock

          const: ref



  resets:

    description:

      At least basic application and reference clock domains resets are

      normally supported by the DWC AHCI SATA controller.

    minItems: 1

    maxItems: 4



  reset-names:

    minItems: 1

    maxItems: 4

    items:

      oneOf:

        - description: Application AHB/AXI BIU clock domain reset control

          enum:

            - arst

            - hrst

        - description: Power Module keep-alive clock domain reset control

          const: pmalive

        - description: RxOOB detection clock domain reset control

          const: rxoob

        - description: Reference clock domain reset control

          const: ref



patternProperties:

  "^sata-port@[0-9a-e]$":

    $ref: '#/$defs/dwc-ahci-port'



additionalProperties: true



$defs:

  dwc-ahci-port:

    $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port



    properties:

      reg:

        minimum: 0

        maximum: 7



      snps,tx-ts-max:

        $ref: /schemas/types.yaml#/definitions/uint32

        description: Maximal size of Tx DMA transactions in FIFO words

        enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]



      snps,rx-ts-max:

        $ref: /schemas/types.yaml#/definitions/uint32

        description: Maximal size of Rx DMA transactions in FIFO words

        enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]



...

Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Synopsys DWC AHCI SATA controller



maintainers:

  - Serge Semin <fancer.lancer@gmail.com>



description:

  This document defines device tree bindings for the generic Synopsys DWC

  implementation of the AHCI SATA controller.



allOf:

  - $ref: snps,dwc-ahci-common.yaml#



properties:

  compatible:

    oneOf:

      - description: Synopsys AHCI SATA-compatible devices

        const: snps,dwc-ahci

      - description: SPEAr1340 AHCI SATA device

        const: snps,spear-ahci

      - description: Rockhip RK3568 AHCI controller

        items:

          - const: rockchip,rk3568-dwc-ahci

          - const: snps,dwc-ahci



patternProperties:

  "^sata-port@[0-9a-e]$":

    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port



    unevaluatedProperties: false



required:

  - compatible

  - reg

  - interrupts



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/ata/ahci.h>



    sata@122f0000 {

      compatible = "snps,dwc-ahci";

      reg = <0x122F0000 0x1ff>;

      #address-cells = <1>;

      #size-cells = <0>;



      interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;



      clocks = <&clock1>, <&clock2>;

      clock-names = "aclk", "ref";



      phys = <&sata_phy>;

      phy-names = "sata-phy";



      ports-implemented = <0x1>;



      sata-port@0 {

        reg = <0>;



        hba-port-cap = <HBA_PORT_FBSCP>;



        snps,tx-ts-max = <512>;

        snps,rx-ts-max = <512>;

      };

    };



...