Commit 5c5dd883 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/qcom' 

- Use correct PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register for v2.7.0
  (Manivannan Sadhasivam)

- Remove "PCIE20_" prefix from register definitions (Manivannan Sadhasivam)

- Sort registers and bitfield declarations (Manivannan Sadhasivam)

- Convert to GENMASK and FIELD_PREP (Manivannan Sadhasivam)

- Use bulk APIs for clocks of IP 1.0.0, 2.3.2, 2.3.3 (Manivannan
  Sadhasivam)

- Use bulk APIs for reset of IP 2.1.0, 2.3.3, 2.4.0 (Manivannan Sadhasivam)

- Rename qcom_pcie_config_sid_sm8250() to be non SM8250-specific
  (Manivannan Sadhasivam)

- Add DT "mhi" register region for supported SoCs (Manivannan Sadhasivam)

- Expose link transition counts via debugfs to help debug low power issues
  (Manivannan Sadhasivam)

- Support system suspend and resume; reduce interconnect bandwidth and turn
  off clock and PHY if there are no active devices (Manivannan Sadhasivam)

- Enable async probe by default to reduce boot time (Manivannan Sadhasivam)

- Add Manivannan Sadhasivam as qcom DT binding maintainer, replacing
  Stanimir Varbanov (Manivannan Sadhasivam)

- Add DT binding and driver support for Qcom SDX55 SoC (Manivannan
  Sadhasivam)

- Add DT binding and driver support for SM8550 SoC (Abel Vesa)

- Document msi-map and msi-map-mask DT properties (Manivannan Sadhasivam)

* pci/controller/qcom:
  dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
  PCI: qcom: Add SM8550 PCIe support
  dt-bindings: PCI: qcom: Add SM8550 compatible
  PCI: qcom: Add support for SDX55 SoC
  dt-bindings: PCI: qcom-ep: Fix the unit address used in example
  dt-bindings: PCI: qcom: Add SDX55 SoC
  dt-bindings: PCI: qcom: Update maintainers entry
  PCI: qcom: Enable async probe by default
  PCI: qcom: Add support for system suspend and resume
  PCI: qcom: Expose link transition counts via debugfs
  dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
  PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
  PCI: qcom: Use macros for defining total no. of clocks & supplies
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
  PCI: qcom: Use lower case for hex
  PCI: qcom: Add missing macros for register fields
  PCI: qcom: Use bitfield definitions for register fields
  PCI: qcom: Sort and group registers and bitfield definitions
  PCI: qcom: Remove PCIE20_ prefix from register definitions
  PCI: qcom: Fix the incorrect register usage in v2.7.0 config
parents b4c85e7b c025c7e5

Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml

+1 −1
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ examples: 
    #include <dt-bindings/clock/qcom,gcc-sdx55.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie_ep: pcie-ep@40000000 {

    pcie_ep: pcie-ep@1c00000 {

        compatible = "qcom,sdx55-pcie-ep";

        reg = <0x01c00000 0x3000>,

              <0x40000000 0xf1d>,

Documentation/devicetree/bindings/pci/qcom,pcie.yaml

+83 −8
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex 


maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>

  - Stanimir Varbanov <svarbanov@mm-sol.com>

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description: |

  Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
@@ -33,22 +33,24 @@ properties: 
          - qcom,pcie-sc8180x

          - qcom,pcie-sc8280xp

          - qcom,pcie-sdm845

          - qcom,pcie-sdx55

          - qcom,pcie-sm8150

          - qcom,pcie-sm8250

          - qcom,pcie-sm8350

          - qcom,pcie-sm8450-pcie0

          - qcom,pcie-sm8450-pcie1

          - qcom,pcie-sm8550

      - items:

          - const: qcom,pcie-msm8998

          - const: qcom,pcie-msm8996



  reg:

    minItems: 4

    maxItems: 5

    maxItems: 6



  reg-names:

    minItems: 4

    maxItems: 5

    maxItems: 6



  interrupts:

    minItems: 1
@@ -58,6 +60,9 @@ properties: 
    minItems: 1

    maxItems: 8



  iommu-map:

    maxItems: 2



  # Common definitions for clocks, clock-names and reset.

  # Platform constraints are described later.

  clocks:
@@ -120,14 +125,20 @@ required: 
  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names

  - "#interrupt-cells"

  - interrupt-map-mask

  - interrupt-map

  - clocks

  - clock-names



anyOf:

  - required:

      - interrupts

      - interrupt-names

      - "#interrupt-cells"

  - required:

      - msi-map

      - msi-map-mask



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#

  - if:
@@ -185,13 +196,15 @@ allOf: 
      properties:

        reg:

          minItems: 4

          maxItems: 4

          maxItems: 5

        reg-names:

          minItems: 4

          items:

            - const: parf # Qualcomm specific registers

            - const: dbi # DesignWare PCIe registers

            - const: elbi # External local bus interface registers

            - const: config # PCIe configuration space

            - const: mhi # MHI registers



  - if:

      properties:
@@ -201,22 +214,26 @@ allOf: 
              - qcom,pcie-sc7280

              - qcom,pcie-sc8180x

              - qcom,pcie-sc8280xp

              - qcom,pcie-sdx55

              - qcom,pcie-sm8250

              - qcom,pcie-sm8350

              - qcom,pcie-sm8450-pcie0

              - qcom,pcie-sm8450-pcie1

              - qcom,pcie-sm8550

    then:

      properties:

        reg:

          minItems: 5

          maxItems: 5

          maxItems: 6

        reg-names:

          minItems: 5

          items:

            - const: parf # Qualcomm specific registers

            - const: dbi # DesignWare PCIe registers

            - const: elbi # External local bus interface registers

            - const: atu # ATU address space

            - const: config # PCIe configuration space

            - const: mhi # MHI registers



  - if:

      properties:
@@ -639,6 +656,37 @@ allOf: 
          items:

            - const: pci # PCIe core reset



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,pcie-sm8550

    then:

      properties:

        clocks:

          minItems: 7

          maxItems: 8

        clock-names:

          minItems: 7

          items:

            - const: aux # Auxiliary clock

            - const: cfg # Configuration clock

            - const: bus_master # Master AXI clock

            - const: bus_slave # Slave AXI clock

            - const: slave_q2a # Slave Q2A clock

            - const: ddrss_sf_tbu # PCIe SF TBU clock

            - const: noc_aggr # Aggre NoC PCIe AXI clock

            - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock

        resets:

          minItems: 1

          maxItems: 2

        reset-names:

          minItems: 1

          items:

            - const: pci # PCIe core reset

            - const: link_down # PCIe link down reset



  - if:

      properties:

        compatible:
@@ -669,6 +717,32 @@ allOf: 
          items:

            - const: pci # PCIe core reset



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,pcie-sdx55

    then:

      properties:

        clocks:

          minItems: 7

          maxItems: 7

        clock-names:

          items:

            - const: pipe # PIPE clock

            - const: aux # Auxiliary clock

            - const: cfg # Configuration clock

            - const: bus_master # Master AXI clock

            - const: bus_slave # Slave AXI clock

            - const: slave_q2a # Slave Q2A clock

            - const: sleep # PCIe Sleep clock

        resets:

          maxItems: 1

        reset-names:

          items:

            - const: pci # PCIe core reset



  - if:

      properties:

        compatible:
@@ -724,6 +798,7 @@ allOf: 
              - qcom,pcie-sm8350

              - qcom,pcie-sm8450-pcie0

              - qcom,pcie-sm8450-pcie1

              - qcom,pcie-sm8550

    then:

      oneOf:

        - properties:

drivers/pci/controller/dwc/pcie-qcom.c

+516 −730

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