Commit 5c1a3768 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: update the method for harvest IP for specific SKU 



Update the method of disabling VCN IP for specific SKU for navi1x ASIC,
it will judge whether should add the related IP at the function of
amdgpu_device_ip_block_add().

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 83a0b863

drivers/gpu/drm/amd/amdgpu/nv.c

+16 −14
Original line number Diff line number Diff line
@@ -623,6 +623,16 @@ static const struct amdgpu_ip_block_version nv_common_ip_block = 
	.funcs = &nv_common_ip_funcs,

};



static bool nv_is_headless_sku(struct pci_dev *pdev)

{

	if ((pdev->device == 0x731E &&

	    (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||

	    (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||

	    (pdev->device == 0x7360 && pdev->revision == 0xC7))

		return true;

	return false;

}



static int nv_reg_base_init(struct amdgpu_device *adev)

{

	int r;
@@ -636,6 +646,10 @@ static int nv_reg_base_init(struct amdgpu_device *adev) 
		}



		amdgpu_discovery_harvest_ip(adev);

		if (nv_is_headless_sku(adev->pdev)) {

			adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;

			adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;

		}



		return 0;

	}
@@ -673,16 +687,6 @@ void nv_set_virt_ops(struct amdgpu_device *adev) 
	adev->virt.ops = &xgpu_nv_virt_ops;

}



static bool nv_is_headless_sku(struct pci_dev *pdev)

{

	if ((pdev->device == 0x731E &&

	    (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||

	    (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||

	    (pdev->device == 0x7360 && pdev->revision == 0xC7))

		return true;

	return false;

}



int nv_set_ip_blocks(struct amdgpu_device *adev)

{

	int r;
@@ -730,7 +734,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (!nv_is_headless_sku(adev->pdev))

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);

		if (adev->enable_mes)
@@ -754,7 +757,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (!nv_is_headless_sku(adev->pdev))

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		if (!amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);