Commit 5c127c85 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Paolo Bonzini
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KVM: SVM: Adding support for configuring x2APIC MSRs interception 



When enabling x2APIC virtualization (x2AVIC), the interception of
x2APIC MSRs must be disabled to let the hardware virtualize guest
MSR accesses.

Current implementation keeps track of list of MSR interception state
in the svm_direct_access_msrs array. Therefore, extends the array to
include x2APIC MSRs.

Reviewed-by: default avatarMaxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Message-Id: <20220519102709.24125-8-suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent ab1b1dc1

arch/x86/kvm/svm/svm.c

+25 −0
Original line number Diff line number Diff line
@@ -100,6 +100,31 @@ static const struct svm_direct_access_msrs { 
	{ .index = MSR_IA32_CR_PAT,			.always = false },

	{ .index = MSR_AMD64_SEV_ES_GHCB,		.always = true  },

	{ .index = MSR_TSC_AUX,				.always = false },

	{ .index = (APIC_BASE_MSR + APIC_ID),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LVR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_TASKPRI),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_ARBPRI),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_PROCPRI),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_EOI),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_RRR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LDR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_DFR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_SPIV),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_ISR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_TMR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_IRR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_ESR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_ICR),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_ICR2),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LVTT),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LVTTHMR),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LVTPC),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LVT0),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LVT1),		.always = false },

	{ .index = (APIC_BASE_MSR + APIC_LVTERR),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_TMICT),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_TMCCT),	.always = false },

	{ .index = (APIC_BASE_MSR + APIC_TDCR),		.always = false },

	{ .index = MSR_INVALID,				.always = false },

};

arch/x86/kvm/svm/svm.h

+2 −2
Original line number Diff line number Diff line
@@ -29,8 +29,8 @@ 
#define	IOPM_SIZE PAGE_SIZE * 3

#define	MSRPM_SIZE PAGE_SIZE * 2



#define MAX_DIRECT_ACCESS_MSRS	21

#define MSRPM_OFFSETS	16

#define MAX_DIRECT_ACCESS_MSRS	46

#define MSRPM_OFFSETS	32

extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;

extern bool npt_enabled;

extern int vgif;