Commit 5bdd3eb2 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdkfd: Remove unused old debugger implementation 



Cleanup the kfd code by removing the unused old debugger
implementation.
The address watch was only ever implemented in the upstream
driver for GFXv7 (Kaveri). The user mode tools runtime using
this API was never open-sourced. Work on the old debugger
prototype that used this API has been discontinued years ago.
Only a small piece of resetting wavefronts is kept and
is moved to kfd_device_queue_manager.c.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6c1a7867

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

+0 −3
Original line number Diff line number Diff line
@@ -37,10 +37,7 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { 
	.hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,

	.hqd_destroy = kgd_gfx_v9_hqd_destroy,

	.hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,

	.address_watch_disable = kgd_gfx_v9_address_watch_disable,

	.address_watch_execute = kgd_gfx_v9_address_watch_execute,

	.wave_control_execute = kgd_gfx_v9_wave_control_execute,

	.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,

	.get_atc_vmid_pasid_mapping_info =

				kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,

	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

+0 −3
Original line number Diff line number Diff line
@@ -289,10 +289,7 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { 
	.hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,

	.hqd_destroy = kgd_gfx_v9_hqd_destroy,

	.hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,

	.address_watch_disable = kgd_gfx_v9_address_watch_disable,

	.address_watch_execute = kgd_gfx_v9_address_watch_execute,

	.wave_control_execute = kgd_gfx_v9_wave_control_execute,

	.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,

	.get_atc_vmid_pasid_mapping_info =

				kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,

	.set_vm_context_page_table_base =

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+0 −24
Original line number Diff line number Diff line
@@ -671,20 +671,6 @@ static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 
	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);

}



static int kgd_address_watch_disable(struct amdgpu_device *adev)

{

	return 0;

}



static int kgd_address_watch_execute(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,

					uint32_t addr_lo)

{

	return 0;

}



static int kgd_wave_control_execute(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)
@@ -709,13 +695,6 @@ static int kgd_wave_control_execute(struct amdgpu_device *adev, 
	return 0;

}



static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return 0;

}



static void set_vm_context_page_table_base(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t page_table_base)

{
@@ -767,10 +746,7 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = { 
	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,

	.hqd_destroy = kgd_hqd_destroy,

	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,

	.address_watch_disable = kgd_address_watch_disable,

	.address_watch_execute = kgd_address_watch_execute,

	.wave_control_execute = kgd_wave_control_execute,

	.address_watch_get_offset = kgd_address_watch_get_offset,

	.get_atc_vmid_pasid_mapping_info =

			get_atc_vmid_pasid_mapping_info,

	.set_vm_context_page_table_base = set_vm_context_page_table_base,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+0 −25
Original line number Diff line number Diff line
@@ -582,21 +582,6 @@ static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd, 
	return 0;

}





static int address_watch_disable_v10_3(struct amdgpu_device *adev)

{

	return 0;

}



static int address_watch_execute_v10_3(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,

					uint32_t addr_lo)

{

	return 0;

}



static int wave_control_execute_v10_3(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)
@@ -621,13 +606,6 @@ static int wave_control_execute_v10_3(struct amdgpu_device *adev, 
	return 0;

}



static uint32_t address_watch_get_offset_v10_3(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return 0;

}



static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t page_table_base)

{
@@ -809,10 +787,7 @@ const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = { 
	.hqd_sdma_is_occupied = hqd_sdma_is_occupied_v10_3,

	.hqd_destroy = hqd_destroy_v10_3,

	.hqd_sdma_destroy = hqd_sdma_destroy_v10_3,

	.address_watch_disable = address_watch_disable_v10_3,

	.address_watch_execute = address_watch_execute_v10_3,

	.wave_control_execute = wave_control_execute_v10_3,

	.address_watch_get_offset = address_watch_get_offset_v10_3,

	.get_atc_vmid_pasid_mapping_info = NULL,

	.set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,

	.program_trap_handler_settings = program_trap_handler_settings_v10_3,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

+0 −96
Original line number Diff line number Diff line
@@ -45,43 +45,6 @@ enum { 
	MAX_WATCH_ADDRESSES = 4

};



enum {

	ADDRESS_WATCH_REG_ADDR_HI = 0,

	ADDRESS_WATCH_REG_ADDR_LO,

	ADDRESS_WATCH_REG_CNTL,

	ADDRESS_WATCH_REG_MAX

};



/*  not defined in the CI/KV reg file  */

enum {

	ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,

	ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,

	ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,

	/* extend the mask to 26 bits to match the low address field */

	ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,

	ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF

};



static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {

	mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,

	mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,

	mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,

	mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL

};



union TCP_WATCH_CNTL_BITS {

	struct {

		uint32_t mask:24;

		uint32_t vmid:4;

		uint32_t atc:1;

		uint32_t mode:2;

		uint32_t valid:1;

	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

			uint32_t queue, uint32_t vmid)

{
@@ -529,55 +492,6 @@ static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, 
	return 0;

}



static int kgd_address_watch_disable(struct amdgpu_device *adev)

{

	union TCP_WATCH_CNTL_BITS cntl;

	unsigned int i;



	cntl.u32All = 0;



	cntl.bitfields.valid = 0;

	cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;

	cntl.bitfields.atc = 1;



	/* Turning off this address until we set all the registers */

	for (i = 0; i < MAX_WATCH_ADDRESSES; i++)

		WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +

			ADDRESS_WATCH_REG_CNTL], cntl.u32All);



	return 0;

}



static int kgd_address_watch_execute(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,

					uint32_t addr_lo)

{

	union TCP_WATCH_CNTL_BITS cntl;



	cntl.u32All = cntl_val;



	/* Turning off this watch point until we set all the registers */

	cntl.bitfields.valid = 0;

	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +

		ADDRESS_WATCH_REG_CNTL], cntl.u32All);



	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +

		ADDRESS_WATCH_REG_ADDR_HI], addr_hi);



	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +

		ADDRESS_WATCH_REG_ADDR_LO], addr_lo);



	/* Enable the watch point */

	cntl.bitfields.valid = 1;



	WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +

		ADDRESS_WATCH_REG_CNTL], cntl.u32All);



	return 0;

}



static int kgd_wave_control_execute(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)
@@ -602,13 +516,6 @@ static int kgd_wave_control_execute(struct amdgpu_device *adev, 
	return 0;

}



static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];

}



static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,

					uint8_t vmid, uint16_t *p_pasid)

{
@@ -665,10 +572,7 @@ const struct kfd2kgd_calls gfx_v7_kfd2kgd = { 
	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,

	.hqd_destroy = kgd_hqd_destroy,

	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,

	.address_watch_disable = kgd_address_watch_disable,

	.address_watch_execute = kgd_address_watch_execute,

	.wave_control_execute = kgd_wave_control_execute,

	.address_watch_get_offset = kgd_address_watch_get_offset,

	.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,

	.set_scratch_backing_va = set_scratch_backing_va,

	.set_vm_context_page_table_base = set_vm_context_page_table_base,