Commit 5bcca743 authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
Browse files

powerpc/perf: Replace raw event hex values with #defines 



Minor cleanup patch to replace the raw event hex values in
power8-pmu.c with #defines.

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 7132e2d6

arch/powerpc/perf/power8-events-list.h

+40 −0
Original line number Diff line number Diff line
@@ -49,3 +49,43 @@ EVENT(PM_L3_PREF_ALL, 0x4e052) 
EVENT(PM_DTLB_MISS,				0x300fc)

/* ITLB Reloaded */

EVENT(PM_ITLB_MISS,				0x400fc)

/* Run_Instructions */

EVENT(PM_RUN_INST_CMPL,				0x500fa)

/* Alternate event code for PM_RUN_INST_CMPL */

EVENT(PM_RUN_INST_CMPL_ALT,			0x400fa)

/* Run_cycles */

EVENT(PM_RUN_CYC,				0x600f4)

/* Alternate event code for Run_cycles */

EVENT(PM_RUN_CYC_ALT,				0x200f4)

/* Marked store completed */

EVENT(PM_MRK_ST_CMPL,				0x10134)

/* Alternate event code for Marked store completed */

EVENT(PM_MRK_ST_CMPL_ALT,			0x301e2)

/* Marked two path branch */

EVENT(PM_BR_MRK_2PATH,				0x10138)

/* Alternate event code for PM_BR_MRK_2PATH */

EVENT(PM_BR_MRK_2PATH_ALT,			0x40138)

/* L3 castouts in Mepf state */

EVENT(PM_L3_CO_MEPF,				0x18082)

/* Alternate event code for PM_L3_CO_MEPF */

EVENT(PM_L3_CO_MEPF_ALT,			0x3e05e)

/* Data cache was reloaded from a location other than L2 due to a marked load */

EVENT(PM_MRK_DATA_FROM_L2MISS,			0x1d14e)

/* Alternate event code for PM_MRK_DATA_FROM_L2MISS */

EVENT(PM_MRK_DATA_FROM_L2MISS_ALT,		0x401e8)

/* Alternate event code for  PM_CMPLU_STALL */

EVENT(PM_CMPLU_STALL_ALT,			0x1e054)

/* Two path branch */

EVENT(PM_BR_2PATH,				0x20036)

/* Alternate event code for PM_BR_2PATH */

EVENT(PM_BR_2PATH_ALT,				0x40036)

/* # PPC Dispatched */

EVENT(PM_INST_DISP,				0x200f2)

/* Alternate event code for PM_INST_DISP */

EVENT(PM_INST_DISP_ALT,				0x300f2)

/* Marked filter Match */

EVENT(PM_MRK_FILT_MATCH,			0x2013c)

/* Alternate event code for PM_MRK_FILT_MATCH */

EVENT(PM_MRK_FILT_MATCH_ALT,			0x3012e)

/* Alternate event code for PM_LD_MISS_L1 */

EVENT(PM_LD_MISS_L1_ALT,			0x400f0)

arch/powerpc/perf/power8-pmu.c

+21 −20
Original line number Diff line number Diff line
@@ -274,7 +274,8 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long 
		/* Ignore Linux defined bits when checking event below */

		base_event = event & ~EVENT_LINUX_MASK;



		if (pmc >= 5 && base_event != 0x500fa && base_event != 0x600f4)

		if (pmc >= 5 && base_event != PM_RUN_INST_CMPL &&

				base_event != PM_RUN_CYC)

			return -1;



		mask  |= CNST_PMC_MASK(pmc);
@@ -488,17 +489,17 @@ static int power8_compute_mmcr(u64 event[], int n_ev, 


/* Table of alternatives, sorted by column 0 */

static const unsigned int event_alternatives[][MAX_ALT] = {

	{ 0x10134, 0x301e2 },		/* PM_MRK_ST_CMPL */

	{ 0x10138, 0x40138 },		/* PM_BR_MRK_2PATH */

	{ 0x18082, 0x3e05e },		/* PM_L3_CO_MEPF */

	{ 0x1d14e, 0x401e8 },		/* PM_MRK_DATA_FROM_L2MISS */

	{ 0x1e054, 0x4000a },		/* PM_CMPLU_STALL */

	{ 0x20036, 0x40036 },		/* PM_BR_2PATH */

	{ 0x200f2, 0x300f2 },		/* PM_INST_DISP */

	{ 0x200f4, 0x600f4 },		/* PM_RUN_CYC */

	{ 0x2013c, 0x3012e },		/* PM_MRK_FILT_MATCH */

	{ 0x3e054, 0x400f0 },		/* PM_LD_MISS_L1 */

	{ 0x400fa, 0x500fa },		/* PM_RUN_INST_CMPL */

	{ PM_MRK_ST_CMPL,		PM_MRK_ST_CMPL_ALT },

	{ PM_BR_MRK_2PATH,		PM_BR_MRK_2PATH_ALT },

	{ PM_L3_CO_MEPF,		PM_L3_CO_MEPF_ALT },

	{ PM_MRK_DATA_FROM_L2MISS,	PM_MRK_DATA_FROM_L2MISS_ALT },

	{ PM_CMPLU_STALL_ALT,		PM_CMPLU_STALL },

	{ PM_BR_2PATH,			PM_BR_2PATH_ALT },

	{ PM_INST_DISP,			PM_INST_DISP_ALT },

	{ PM_RUN_CYC_ALT,		PM_RUN_CYC },

	{ PM_MRK_FILT_MATCH,		PM_MRK_FILT_MATCH_ALT },

	{ PM_LD_MISS_L1,		PM_LD_MISS_L1_ALT },

	{ PM_RUN_INST_CMPL_ALT,		PM_RUN_INST_CMPL },

};



/*
@@ -546,17 +547,17 @@ static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 
		j = num_alt;

		for (i = 0; i < num_alt; ++i) {

			switch (alt[i]) {

			case 0x1e:	/* PM_CYC */

				alt[j++] = 0x600f4;	/* PM_RUN_CYC */

			case PM_CYC:

				alt[j++] = PM_RUN_CYC;

				break;

			case 0x600f4:	/* PM_RUN_CYC */

				alt[j++] = 0x1e;

			case PM_RUN_CYC:

				alt[j++] = PM_CYC;

				break;

			case 0x2:	/* PM_PPC_CMPL */

				alt[j++] = 0x500fa;	/* PM_RUN_INST_CMPL */

			case PM_INST_CMPL:

				alt[j++] = PM_RUN_INST_CMPL;

				break;

			case 0x500fa:	/* PM_RUN_INST_CMPL */

				alt[j++] = 0x2;	/* PM_PPC_CMPL */

			case PM_RUN_INST_CMPL:

				alt[j++] = PM_INST_CMPL;

				break;

			}

		}