Commit 5b6b7806 authored by Ohad Sharabi's avatar Ohad Sharabi Committed by Oded Gabbay
Browse files

habanalabs: update security map after init CPU Qs 



when reading CPU_BOOT_DEV_STS0 reg after FW reports SRAM AVAILABLE the
value in the register might not yet be updated by FW.
to overcome this issue another "up-to-date" read of this register is
done at the end of CPU queues init.

Signed-off-by: default avatarOhad Sharabi <osharabi@habana.ai>
Reviewed-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent 28bcf1fd

drivers/misc/habanalabs/common/firmware_if.c

+2 −5
Original line number Diff line number Diff line
@@ -125,7 +125,8 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, 
		goto out;

	}



	if (hdev->asic_prop.fw_cpucp_ack_with_pi)

	if (hdev->asic_prop.fw_app_security_map &

			CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN)

		expected_ack_val = queue->pi;

	else

		expected_ack_val = CPUCP_PACKET_FENCE_VAL;
@@ -786,10 +787,6 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, 
				CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)

			prop->hard_reset_done_by_fw = true;



		if (prop->fw_boot_cpu_security_map &

				CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN)

			prop->fw_cpucp_ack_with_pi = true;



		dev_dbg(hdev->dev,

			"Firmware boot CPU security status %#x\n",

			prop->fw_boot_cpu_security_map);

drivers/misc/habanalabs/common/habanalabs.h

+0 −3
Original line number Diff line number Diff line
@@ -420,8 +420,6 @@ struct hl_mmu_properties { 
 *                            from BOOT_DEV_STS0

 * @dram_supports_virtual_memory: is there an MMU towards the DRAM

 * @hard_reset_done_by_fw: true if firmware is handling hard reset flow

 * @fw_cpucp_ack_with_pi: true if cpucp is acking messages with the PQ PI

 *                        instead of a magic number

 * @num_functional_hbms: number of functional HBMs in each DCORE.

 */

struct asic_fixed_properties {
@@ -483,7 +481,6 @@ struct asic_fixed_properties { 
	u8				fw_security_status_valid;

	u8				dram_supports_virtual_memory;

	u8				hard_reset_done_by_fw;

	u8				fw_cpucp_ack_with_pi;

	u8				num_functional_hbms;

};

drivers/misc/habanalabs/gaudi/gaudi.c

+5 −1
Original line number Diff line number Diff line
@@ -536,7 +536,6 @@ static int gaudi_get_fixed_properties(struct hl_device *hdev) 
	prop->fw_security_disabled = true;

	prop->fw_security_status_valid = false;

	prop->hard_reset_done_by_fw = false;

	prop->fw_cpucp_ack_with_pi = false;



	return 0;

}
@@ -3727,6 +3726,7 @@ static int gaudi_init_cpu(struct hl_device *hdev) 
static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout)

{

	struct gaudi_device *gaudi = hdev->asic_specific;

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	struct hl_eq *eq;

	u32 status;

	struct hl_hw_queue *cpu_pq =
@@ -3783,6 +3783,10 @@ static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout) 
		return -EIO;

	}



	/* update FW application security bits */

	if (prop->fw_security_status_valid)

		prop->fw_app_security_map = RREG32(mmCPU_BOOT_DEV_STS0);



	gaudi->hw_cap_initialized |= HW_CAP_CPU_Q;

	return 0;

}

drivers/misc/habanalabs/goya/goya.c

+5 −1
Original line number Diff line number Diff line
@@ -464,7 +464,6 @@ int goya_get_fixed_properties(struct hl_device *hdev) 
	prop->fw_security_disabled = true;

	prop->fw_security_status_valid = false;

	prop->hard_reset_done_by_fw = false;

	prop->fw_cpucp_ack_with_pi = false;



	return 0;

}
@@ -1189,6 +1188,7 @@ static int goya_stop_external_queues(struct hl_device *hdev) 
int goya_init_cpu_queues(struct hl_device *hdev)

{

	struct goya_device *goya = hdev->asic_specific;

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	struct hl_eq *eq;

	u32 status;

	struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
@@ -1241,6 +1241,10 @@ int goya_init_cpu_queues(struct hl_device *hdev) 
		return -EIO;

	}



	/* update FW application security bits */

	if (prop->fw_security_status_valid)

		prop->fw_app_security_map = RREG32(mmCPU_BOOT_DEV_STS0);



	goya->hw_cap_initialized |= HW_CAP_CPU_Q;

	return 0;

}