Loading drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +2 −0 Original line number Diff line number Diff line Loading @@ -1426,6 +1426,8 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) if (grctx->r419cb8) grctx->r419cb8(gr); if (grctx->r418800) grctx->r418800(gr); } #define CB_RESERVED 0x80000 Loading drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +2 −0 Original line number Diff line number Diff line Loading @@ -65,6 +65,7 @@ struct gf100_grctx_func { void (*smid_config)(struct gf100_gr *); /* misc other things */ void (*r419cb8)(struct gf100_gr *); void (*r418800)(struct gf100_gr *); }; extern const struct gf100_grctx_func gf100_grctx; Loading Loading @@ -107,6 +108,7 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *); void gk104_grctx_generate_pagepool(struct gf100_grctx *); void gk104_grctx_generate_patch_ltc(struct gf100_grctx *); void gk104_grctx_generate_unkn(struct gf100_gr *); void gk104_grctx_generate_r418800(struct gf100_gr *); extern const struct gf100_grctx_func gk110_grctx; extern const struct gf100_grctx_func gk110b_grctx; Loading drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +17 −2 Original line number Diff line number Diff line Loading @@ -840,6 +840,21 @@ gk104_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ void gk104_grctx_generate_r418800(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; /*XXX: Not real sure where to apply these, there doesn't seem * to be any pattern to which chipsets it's done on. * * Perhaps a VBIOS tweak? */ if (0) { nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); } } void gk104_grctx_generate_patch_ltc(struct gf100_grctx *info) { Loading Loading @@ -935,8 +950,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mthd(gr, grctx->mthd); nvkm_mc_unk260(device, 1); nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); grctx->r418800(gr); } void Loading Loading @@ -1016,4 +1030,5 @@ gk104_grctx = { .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r419f78 = gk104_grctx_generate_r419f78, .r418800 = gk104_grctx_generate_r418800, }; drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c +1 −0 Original line number Diff line number Diff line Loading @@ -837,4 +837,5 @@ gk110_grctx = { .alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables, .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, }; drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c +1 −0 Original line number Diff line number Diff line Loading @@ -98,4 +98,5 @@ gk110b_grctx = { .alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables, .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, }; Loading
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +2 −0 Original line number Diff line number Diff line Loading @@ -1426,6 +1426,8 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) if (grctx->r419cb8) grctx->r419cb8(gr); if (grctx->r418800) grctx->r418800(gr); } #define CB_RESERVED 0x80000 Loading
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +2 −0 Original line number Diff line number Diff line Loading @@ -65,6 +65,7 @@ struct gf100_grctx_func { void (*smid_config)(struct gf100_gr *); /* misc other things */ void (*r419cb8)(struct gf100_gr *); void (*r418800)(struct gf100_gr *); }; extern const struct gf100_grctx_func gf100_grctx; Loading Loading @@ -107,6 +108,7 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *); void gk104_grctx_generate_pagepool(struct gf100_grctx *); void gk104_grctx_generate_patch_ltc(struct gf100_grctx *); void gk104_grctx_generate_unkn(struct gf100_gr *); void gk104_grctx_generate_r418800(struct gf100_gr *); extern const struct gf100_grctx_func gk110_grctx; extern const struct gf100_grctx_func gk110b_grctx; Loading
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +17 −2 Original line number Diff line number Diff line Loading @@ -840,6 +840,21 @@ gk104_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ void gk104_grctx_generate_r418800(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; /*XXX: Not real sure where to apply these, there doesn't seem * to be any pattern to which chipsets it's done on. * * Perhaps a VBIOS tweak? */ if (0) { nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); } } void gk104_grctx_generate_patch_ltc(struct gf100_grctx *info) { Loading Loading @@ -935,8 +950,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mthd(gr, grctx->mthd); nvkm_mc_unk260(device, 1); nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); grctx->r418800(gr); } void Loading Loading @@ -1016,4 +1030,5 @@ gk104_grctx = { .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r419f78 = gk104_grctx_generate_r419f78, .r418800 = gk104_grctx_generate_r418800, };
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c +1 −0 Original line number Diff line number Diff line Loading @@ -837,4 +837,5 @@ gk110_grctx = { .alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables, .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, };
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c +1 −0 Original line number Diff line number Diff line Loading @@ -98,4 +98,5 @@ gk110b_grctx = { .alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables, .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, };