Commit 5b247d93 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-phy-QUSGMII' 



Maxime Chevallier says:

====================
net: Introduce QUSGMII phy mode

Re-sending, since the previous v4 was sent while net-next was closed.

This is a resend of the V4 of a previous series [1] initially aimed at
introducing inband extensions, with modes like QUSGMII. This mode allows
passing info in the ethernet preamble between the MAC and the PHY, such as
timestamps.

This series has now become a preliminary series, that simply introduces
the new interface mode, without support for inband extensions, that will
come later.

The reasonning is that work will need to be done in the networking
subsystem, but also in the generic phy driver subsystem to allow serdes
configuration for qusgmii.

This series add the mode, the relevant binding changes, adds support for
it in the lan966x driver, and also introduces a small helper to get the
number of links a given phy mode can carry (think 1 for SGMII and 4 for
QSGMII). This allows for better readability and will prove useful
when (if) we support PSGMII (5 links on 1 interface) and OUSGMII (8
links on one interface).

V4 contains no change but the collected Reviewed-by from Andrew.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d04807b8 ac0167fb

Documentation/devicetree/bindings/net/ethernet-controller.yaml

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ properties: 
      - gmii

      - sgmii

      - qsgmii

      - qusgmii

      - tbi

      - rev-mii

      - rmii

Documentation/networking/phy.rst

+9 −0
Original line number Diff line number Diff line
@@ -308,6 +308,15 @@ Some of the interface modes are described below: 
    rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying

    data rate of 100Mpbs.



``PHY_INTERFACE_MODE_QUSGMII``

    This defines the Cisco the Quad USGMII mode, which is the Quad variant of

    the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses

    a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not

    only the port id, but also so-called "extensions". The only documented

    extension so-far in the specification is the inclusion of timestamps, for

    PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the

    same capabilities in terms of link speed and negociation.



Pause frames / flow control

===========================

drivers/net/ethernet/microchip/lan966x/lan966x_main.c

+2 −0
Original line number Diff line number Diff line
@@ -778,6 +778,8 @@ static int lan966x_probe_port(struct lan966x *lan966x, u32 p, 
		  port->phylink_config.supported_interfaces);

	__set_bit(PHY_INTERFACE_MODE_QSGMII,

		  port->phylink_config.supported_interfaces);

	__set_bit(PHY_INTERFACE_MODE_QUSGMII,

		  port->phylink_config.supported_interfaces);

	__set_bit(PHY_INTERFACE_MODE_1000BASEX,

		  port->phylink_config.supported_interfaces);

	__set_bit(PHY_INTERFACE_MODE_2500BASEX,

drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c

+2 −1
Original line number Diff line number Diff line
@@ -28,11 +28,12 @@ static int lan966x_phylink_mac_prepare(struct phylink_config *config, 
				       phy_interface_t iface)

{

	struct lan966x_port *port = netdev_priv(to_net_dev(config->dev));

	phy_interface_t serdes_mode = iface;

	int err;



	if (port->serdes) {

		err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET,

				       iface);

				       serdes_mode);

		if (err) {

			netdev_err(to_net_dev(config->dev),

				   "Could not set mode of SerDes\n");

drivers/net/ethernet/microchip/lan966x/lan966x_port.c

+16 −6
Original line number Diff line number Diff line
@@ -168,7 +168,7 @@ static void lan966x_port_link_up(struct lan966x_port *port) 
	/* Also the GIGA_MODE_ENA(1) needs to be set regardless of the

	 * port speed for QSGMII ports.

	 */

	if (config->portmode == PHY_INTERFACE_MODE_QSGMII)

	if (phy_interface_num_ports(config->portmode) == 4)

		mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1);



	lan_wr(config->duplex | mode,
@@ -331,10 +331,14 @@ int lan966x_port_pcs_set(struct lan966x_port *port, 
	struct lan966x *lan966x = port->lan966x;

	bool inband_aneg = false;

	bool outband;

	bool full_preamble = false;



	if (config->portmode == PHY_INTERFACE_MODE_QUSGMII)

		full_preamble = true;



	if (config->inband) {

		if (config->portmode == PHY_INTERFACE_MODE_SGMII ||

		    config->portmode == PHY_INTERFACE_MODE_QSGMII)

		    phy_interface_num_ports(config->portmode) == 4)

			inband_aneg = true; /* Cisco-SGMII in-band-aneg */

		else if (config->portmode == PHY_INTERFACE_MODE_1000BASEX &&

			 config->autoneg)
@@ -345,9 +349,15 @@ int lan966x_port_pcs_set(struct lan966x_port *port, 
		outband = true;

	}



	/* Disable or enable inband */

	lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband),

		DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA,

	/* Disable or enable inband.

	 * For QUSGMII, we rely on the preamble to transmit data such as

	 * timestamps, therefore force full preamble transmission, and prevent

	 * premable shortening

	 */

	lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband) |

		DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(full_preamble),

		DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA |

		DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA,

		lan966x, DEV_PCS1G_MODE_CFG(port->chip_port));



	/* Enable PCS */
@@ -396,7 +406,7 @@ void lan966x_port_init(struct lan966x_port *port) 
	if (lan966x->fdma)

		lan966x_fdma_netdev_init(lan966x, port->dev);



	if (config->portmode != PHY_INTERFACE_MODE_QSGMII)

	if (phy_interface_num_ports(config->portmode) != 4)

		return;



	lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |