Commit 5b109397 authored by Jude Shih's avatar Jude Shih Committed by Alex Deucher
Browse files

drm/amd/display: Enable dpia in dmub only for DCN31 B0 



[Why]
DMUB binary is common for both A0 and B0. Hence, driver should
notify FW about the support for DPIA in B0.

[How]
Added dpia_supported bit in dmub_fw_boot_options and will be set
only for B0.

Assign dpia_supported to true before dm_dmub_hw_init
in B0 case.

v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex)

Signed-off-by: default avatarJude Shih <shenshih@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 094b21c1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+14 −0
Original line number Original line Diff line number Diff line
@@ -1017,6 +1017,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) 
	const unsigned char *fw_inst_const, *fw_bss_data;

	const unsigned char *fw_inst_const, *fw_bss_data;

	uint32_t i, fw_inst_const_size, fw_bss_data_size;

	uint32_t i, fw_inst_const_size, fw_bss_data_size;

	bool has_hw_support;

	bool has_hw_support;

	struct dc *dc = adev->dm.dc;





	if (!dmub_srv)

	if (!dmub_srv)

		/* DMUB isn't supported on the ASIC. */

		/* DMUB isn't supported on the ASIC. */
@@ -1103,6 +1104,19 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) 
	for (i = 0; i < fb_info->num_fb; ++i)

	for (i = 0; i < fb_info->num_fb; ++i)

		hw_params.fb[i] = &fb_info->fb[i];

		hw_params.fb[i] = &fb_info->fb[i];





	switch (adev->asic_type) {

	case CHIP_YELLOW_CARP:

		if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {

			hw_params.dpia_supported = true;

#if defined(CONFIG_DRM_AMD_DC_DCN)

			hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;

#endif

		}

		break;

	default:

		break;

	}



	status = dmub_srv_hw_init(dmub_srv, &hw_params);

	status = dmub_srv_hw_init(dmub_srv, &hw_params);

	if (status != DMUB_STATUS_OK) {

	if (status != DMUB_STATUS_OK) {

		DRM_ERROR("Error initializing DMUB HW: %d\n", status);

		DRM_ERROR("Error initializing DMUB HW: %d\n", status);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -238,6 +238,7 @@ struct dmub_srv_hw_params { 
	bool load_inst_const;

	bool load_inst_const;

	bool skip_panel_power_sequence;

	bool skip_panel_power_sequence;

	bool disable_z10;

	bool disable_z10;

	bool dpia_supported;

	bool disable_dpia;

	bool disable_dpia;

};

};

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -338,6 +338,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu 
	union dmub_fw_boot_options boot_options = {0};

	union dmub_fw_boot_options boot_options = {0};





	boot_options.bits.z10_disable = params->disable_z10;

	boot_options.bits.z10_disable = params->disable_z10;

	boot_options.bits.dpia_supported = params->dpia_supported;

	boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;

	boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;





	boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;

	boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;