Commit 5b06dcfd authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
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arm64/fp: Rename SVE and SME LEN field name to _WIDTH 



The SVE and SVE length configuration field LEN have constants specifying
their width called _SIZE rather than the more normal _WIDTH, in preparation
for automatic generation rename to _WIDTH. No functional change.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220510161208.631259-3-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent f171f9e4

arch/arm64/include/asm/sysreg.h

+2 −2
Original line number Diff line number Diff line
@@ -1114,14 +1114,14 @@ 
#define DCZID_BS_SHIFT			0



#define ZCR_ELx_LEN_SHIFT	0

#define ZCR_ELx_LEN_SIZE	4

#define ZCR_ELx_LEN_WIDTH	4

#define ZCR_ELx_LEN_MASK	0xf



#define SMCR_ELx_FA64_SHIFT	31

#define SMCR_ELx_FA64_MASK	(1 << SMCR_ELx_FA64_SHIFT)



#define SMCR_ELx_LEN_SHIFT	0

#define SMCR_ELx_LEN_SIZE	4

#define SMCR_ELx_LEN_WIDTH	4

#define SMCR_ELx_LEN_MASK	0xf



#define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */

arch/arm64/kernel/cpufeature.c

+2 −2
Original line number Diff line number Diff line
@@ -577,13 +577,13 @@ static const struct arm64_ftr_bits ftr_id_dfr1[] = { 


static const struct arm64_ftr_bits ftr_zcr[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,

		ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),	/* LEN */

		ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0),	/* LEN */

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_smcr[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,

		SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_SIZE, 0),	/* LEN */

		SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0),	/* LEN */

	ARM64_FTR_END,

};