Unverified Commit 5b017b5e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v6.4-rockchip-dtsfixes1' of... 

Merge tag 'v6.4-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes

Fixes for the reset pin on nanopi r5c, a reset line on SOQuartz, a duplicate
usb regulator on rock64 and PCIe register mappings on rk356x.
Also some missing cache properties.

* tag 'v6.4-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Fix rk356x PCIe register and range mappings
  arm64: dts: rockchip: fix button reset pin for nanopi r5c
  arm64: dts: rockchip: fix nEXTRST on SOQuartz
  arm64: dts: rockchip: add missing cache properties
  arm64: dts: rockchip: fix USB regulator on ROCK64

Link: https://lore.kernel.org/r/2885657.e9J7NaK4W3@phil


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 858fd168 568a67e7

arch/arm64/boot/dts/rockchip/rk3308.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ 
		l2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/rockchip/rk3328-rock64.dts

+2 −12
Original line number Diff line number Diff line
@@ -37,7 +37,8 @@ 
		vin-supply = <&vcc_io>;

	};



	vcc_host_5v: vcc-host-5v-regulator {

	/* Common enable line for all of the rails mentioned in the labels */

	vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator {

		compatible = "regulator-fixed";

		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;

		pinctrl-names = "default";
@@ -48,17 +49,6 @@ 
		vin-supply = <&vcc_sys>;

	};



	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {

		compatible = "regulator-fixed";

		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;

		pinctrl-names = "default";

		pinctrl-0 = <&usb20_host_drv>;

		regulator-name = "vcc_host1_5v";

		regulator-always-on;

		regulator-boot-on;

		vin-supply = <&vcc_sys>;

	};



	vcc_sys: vcc-sys {

		compatible = "regulator-fixed";

		regulator-name = "vcc_sys";

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts

+11 −7
Original line number Diff line number Diff line
@@ -28,6 +28,16 @@ 
		regulator-max-microvolt = <5000000>;

		vin-supply = <&vcc12v_dcin>;

	};



	vcc_sd_pwr: vcc-sd-pwr-regulator {

		compatible = "regulator-fixed";

		regulator-name = "vcc_sd_pwr";

		regulator-always-on;

		regulator-boot-on;

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc3v3_sys>;

	};

};



/* phy for pcie */
@@ -130,13 +140,7 @@ 
};



&sdmmc0 {

	vmmc-supply = <&sdmmc_pwr>;

	status = "okay";

};



&sdmmc_pwr {

	regulator-min-microvolt = <3300000>;

	regulator-max-microvolt = <3300000>;

	vmmc-supply = <&vcc_sd_pwr>;

	status = "okay";

};

arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi

+13 −16
Original line number Diff line number Diff line
@@ -104,16 +104,6 @@ 
		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc5v0_sys>;

	};



	sdmmc_pwr: sdmmc-pwr-regulator {

		compatible = "regulator-fixed";

		enable-active-high;

		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&sdmmc_pwr_h>;

		regulator-name = "sdmmc_pwr";

		status = "disabled";

	};

};



&cpu0 {
@@ -155,6 +145,19 @@ 
	status = "disabled";

};



&gpio0 {

	nextrst-hog {

		gpio-hog;

		/*

		 * GPIO_ACTIVE_LOW + output-low here means that the pin is set

		 * to high, because output-low decides the value pre-inversion.

		 */

		gpios = <RK_PA5 GPIO_ACTIVE_LOW>;

		line-name = "nEXTRST";

		output-low;

	};

};



&gpu {

	mali-supply = <&vdd_gpu>;

	status = "okay";
@@ -538,12 +541,6 @@ 
			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};



	sdmmc-pwr {

		sdmmc_pwr_h: sdmmc-pwr-h {

			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};

};



&pmu_io_domains {