Commit 5af5169d authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Convert INTEL_INFO()->display to a pointer 



Rather than embeddeding the display's device info within the main device
info structure, just provide a pointer to the display-specific
structure.  This is in preparation for moving the display device info
definitions into the display code itself and for eventually allowing the
pointer to be assigned at runtime on platforms that use GMD_ID for
device identification.

In the future, this will also eventually allow the same display device
info structures to be used outside the current i915 code (e.g., from the
Xe driver).

v2:
 - Move introduction of DISPLAY_INFO() to this patch.  (Andrzej)
v3:
 - Also use DISPLAY_INFO() in intel_display_reg_defs.h.  (Andrzej)
 - Use "{}" instead of "{ 0 }" for empty struct init.  (Jani)

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Acked-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230523195609.73627-3-matthew.d.roper@intel.com
parent 05aa8e01

drivers/gpu/drm/i915/display/intel_color.c

+16 −15
Original line number Diff line number Diff line
@@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state) 
	if (lut_is_legacy(gamma_lut))

		return 0;



	return INTEL_INFO(i915)->display.color.gamma_lut_tests;

	return DISPLAY_INFO(i915)->color.gamma_lut_tests;

}



static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);



	return INTEL_INFO(i915)->display.color.degamma_lut_tests;

	return DISPLAY_INFO(i915)->color.degamma_lut_tests;

}



static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
@@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state) 
	if (lut_is_legacy(gamma_lut))

		return LEGACY_LUT_LENGTH;



	return INTEL_INFO(i915)->display.color.gamma_lut_size;

	return DISPLAY_INFO(i915)->color.gamma_lut_size;

}



static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);



	return INTEL_INFO(i915)->display.color.degamma_lut_size;

	return DISPLAY_INFO(i915)->color.degamma_lut_size;

}



static int check_lut_size(const struct drm_property_blob *lut, int expected)
@@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state *crtc_state) 
		struct drm_property_blob *gamma_lut;



		gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,

					       INTEL_INFO(i915)->display.color.degamma_lut_size,

					       DISPLAY_INFO(i915)->color.degamma_lut_size,

					       false);

		if (IS_ERR(gamma_lut))

			return PTR_ERR(gamma_lut);
@@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) 
static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	u32 lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	int i, lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state) 
static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;

	int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -2980,7 +2980,7 @@ static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc) 
static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)

{

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;

	int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -3044,7 +3044,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) 
static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)

{

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;

	int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -3228,7 +3228,7 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state) 
static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;

	int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -3293,7 +3293,7 @@ static struct drm_property_blob * 
icl_read_lut_multi_segment(struct intel_crtc *crtc)

{

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;

	int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -3471,8 +3471,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc) 


	drm_mode_crtc_set_gamma_size(&crtc->base, 256);



	gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;

	degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;

	gamma_lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;

	degamma_lut_size = DISPLAY_INFO(i915)->color.degamma_lut_size;

	has_ctm = degamma_lut_size != 0;



	/*
@@ -3497,7 +3497,8 @@ int intel_color_init(struct drm_i915_private *i915) 
	if (DISPLAY_VER(i915) != 10)

		return 0;



	blob = create_linear_lut(i915, INTEL_INFO(i915)->display.color.degamma_lut_size);

	blob = create_linear_lut(i915,

				 DISPLAY_INFO(i915)->color.degamma_lut_size);

	if (IS_ERR(blob))

		return PTR_ERR(blob);

drivers/gpu/drm/i915/display/intel_cursor.c

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 
	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);

	u32 base;



	if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)

	if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)

		base = sg_dma_address(obj->mm.pages->sgl);

	else

		base = intel_plane_ggtt_offset(plane_state);

drivers/gpu/drm/i915/display/intel_display.h

+1 −1
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ enum i9xx_plane_id { 


#define for_each_dbuf_slice(__dev_priv, __slice) \

	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \

		for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))

		for_each_if(INTEL_INFO(__dev_priv)->display->dbuf.slice_mask & BIT(__slice))



#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \

	for_each_dbuf_slice((__dev_priv), (__slice)) \

drivers/gpu/drm/i915/display/intel_display_power.c

+3 −3
Original line number Diff line number Diff line
@@ -1053,7 +1053,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 
			     u8 req_slices)

{

	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;

	u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;

	u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask;

	enum dbuf_slice slice;



	drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
@@ -1113,7 +1113,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) 


static void icl_mbus_init(struct drm_i915_private *dev_priv)

{

	unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;

	unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask;

	u32 mask, val, i;



	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
@@ -1568,7 +1568,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) 
	enum intel_dram_type type = dev_priv->dram_info.type;

	u8 num_channels = dev_priv->dram_info.num_channels;

	const struct buddy_page_mask *table;

	unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;

	unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask;

	int config, i;



	/* BW_BUDDY registers are not used on dgpu's beyond DG1 */

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

+7 −7
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include "i915_reg_defs.h"



#define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display.mmio_offset)

#define DISPLAY_MMIO_BASE(dev_priv)	(DISPLAY_INFO(dev_priv)->mmio_offset)



#define VLV_DISPLAY_BASE		0x180000
@@ -36,14 +36,14 @@ 
 * Device info offset array based helpers for groups of registers with unevenly

 * spaced base offsets.

 */

#define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \

					      INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \

#define _MMIO_PIPE2(pipe, reg)		_MMIO(DISPLAY_INFO(dev_priv)->pipe_offsets[(pipe)] - \

					      DISPLAY_INFO(dev_priv)->pipe_offsets[PIPE_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))

#define _MMIO_TRANS2(tran, reg)		_MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \

					      INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \

#define _MMIO_TRANS2(tran, reg)		_MMIO(DISPLAY_INFO(dev_priv)->trans_offsets[(tran)] - \

					      DISPLAY_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))

#define _MMIO_CURSOR2(pipe, reg)	_MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \

					      INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \

#define _MMIO_CURSOR2(pipe, reg)	_MMIO(DISPLAY_INFO(dev_priv)->cursor_offsets[(pipe)] - \

					      DISPLAY_INFO(dev_priv)->cursor_offsets[PIPE_A] + \

					      DISPLAY_MMIO_BASE(dev_priv) + (reg))



#endif /* __INTEL_DISPLAY_REG_DEFS_H__ */