Commit 5ae3e744 authored by David Hildenbrand's avatar David Hildenbrand Committed by Andrew Morton
Browse files

openrisc/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE 

Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit from the
type.  Generic MM currently only uses 5 bits for the type
(MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused.

While at it, mask the type in __swp_entry().

Link: https://lkml.kernel.org/r/20230113171026.582290-16-david@redhat.com


Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent 4d1d955f

arch/openrisc/include/asm/pgtable.h

+36 −5
Original line number Diff line number Diff line
@@ -154,6 +154,9 @@ extern void paging_init(void); 
#define _KERNPG_TABLE \

	(_PAGE_BASE | _PAGE_SRE | _PAGE_SWE | _PAGE_ACCESSED | _PAGE_DIRTY)



/* We borrow bit 11 to store the exclusive marker in swap PTEs. */

#define _PAGE_SWP_EXCLUSIVE	_PAGE_U_SHARED



#define PAGE_NONE       __pgprot(_PAGE_ALL)

#define PAGE_READONLY   __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)

#define PAGE_READONLY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
@@ -385,16 +388,44 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, 


/* __PHX__ FIXME, SWAP, this probably doesn't work */



/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */

/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */



#define __swp_type(x)			(((x).val >> 5) & 0x7f)

/*

 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that

 * are !pte_none() && !pte_present().

 *

 * Format of swap PTEs:

 *

 *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1

 *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

 *   <-------------- offset ---------------> E <- type --> 0 0 0 0 0

 *

 *   E is the exclusive marker that is not stored in swap entries.

 *   The zero'ed bits include _PAGE_PRESENT.

 */

#define __swp_type(x)			(((x).val >> 5) & 0x3f)

#define __swp_offset(x)			((x).val >> 12)

#define __swp_entry(type, offset) \

	((swp_entry_t) { ((type) << 5) | ((offset) << 12) })

	((swp_entry_t) { (((type) & 0x3f) << 5) | ((offset) << 12) })

#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })

#define __swp_entry_to_pte(x)		((pte_t) { (x).val })



#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE

static inline int pte_swp_exclusive(pte_t pte)

{

	return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;

}



static inline pte_t pte_swp_mkexclusive(pte_t pte)

{

	pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;

	return pte;

}



static inline pte_t pte_swp_clear_exclusive(pte_t pte)

{

	pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;

	return pte;

}



typedef pte_t *pte_addr_t;



#endif /* __ASSEMBLY__ */