Commit 5add4575 authored by Ankit Nautiyal's avatar Ankit Nautiyal Committed by Imre Deak
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drm/i915/ddi: Align timeout for DDI_BUF_CTL active with Bspec 



For Gen12+ wait for 1ms for Combo Phy and 3ms for TC Phy for
DDI_BUF_CTL to be active for TC phy. (Bspec:49190)

v2: Minor refactoring for better readability.

v3: Rebased and retained the order of checking platforms. (Imre)

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221207145436.1510625-1-ankit.k.nautiyal@intel.com
parent f087cfe6

drivers/gpu/drm/i915/display/intel_ddi.c

+14 −1
Original line number Diff line number Diff line
@@ -185,6 +185,8 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 
static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,

				      enum port port)

{

	enum phy phy = intel_port_to_phy(dev_priv, port);

	int timeout_us;

	int ret;



	/* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
@@ -193,8 +195,19 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 
		return;

	}



	if (IS_DG2(dev_priv)) {

		timeout_us = 1200;

	} else if (DISPLAY_VER(dev_priv) >= 12) {

		if (intel_phy_is_tc(dev_priv, phy))

			timeout_us = 3000;

		else

			timeout_us = 1000;

	} else {

		timeout_us = 500;

	}



	ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &

			  DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);

			  DDI_BUF_IS_IDLE), timeout_us, 10, 10);



	if (ret)

		drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",