Commit 5ac84806 authored by Swathi Dhanavanthri's avatar Swathi Dhanavanthri Committed by Lucas De Marchi
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drm/i915/tgl, rkl, dg1: Apply WA_1406941453 to TGL, RKL and DG1



This workaround is applicable only for tgl,rkl and dg1.

Bspec: 52890, 53273, 53508.

Signed-off-by: default avatarSwathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Reviewed-by: default avatarClint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201201175735.1377372-1-lucas.demarchi@intel.com
parent cb2ce93e
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+5 −7
Original line number Diff line number Diff line
@@ -1778,6 +1778,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
		wa_masked_en(wal,
			     GEN9_CS_DEBUG_MODE1,
			     FF_DOP_CLOCK_GATE_DISABLE);

		/* Wa_1406941453:tgl,rkl,dg1 */
		wa_masked_en(wal,
			     GEN10_SAMPLER_MODE,
			     ENABLE_SMALLPL);
	}

	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
@@ -1808,13 +1813,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
	}

	if (IS_GEN(i915, 12)) {
		/* Wa_1406941453:gen12 */
		wa_masked_en(wal,
			     GEN10_SAMPLER_MODE,
			     ENABLE_SMALLPL);
	}

	if (IS_GEN(i915, 11)) {
		/* This is not an Wa. Enable for better image quality */
		wa_masked_en(wal,