Commit 5ac421a9 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Give CPU transcoder timing registers TRANS_ prefix 



Name the CPU transcoder timing registers TRANS_FOO rather than
just FOO. This is the modern name, after the pipe/transcoder split
happened. Makes it a bit more obvious whether you pass in a pipe or
a transcoder.

PIPESRC is a bit special as it's a pipe register, even though it
lives in the transcoder registers range (0x60000 instead of 0x70000).

And BCLRPAT I suppose is a transcoder register (since it has something
to do with the timing generator), but it doesn't even exist after gen4
so I left it to use the only name it ever had in bspec.

And while at it let's pass in the correct enum in few more
places why don't we. Although in all those places the distinction
doesn't matter.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-4-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 48630a31

drivers/gpu/drm/i915/display/icl_dsi.c

+6 −6
Original line number Diff line number Diff line
@@ -887,7 +887,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	/* program TRANS_HTOTAL register */

	for_each_dsi_port(port, intel_dsi->ports) {

		dsi_trans = dsi_port_to_transcoder(port);

		intel_de_write(dev_priv, HTOTAL(dsi_trans),

		intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),

			       (hactive - 1) | ((htotal - 1) << 16));

	}
@@ -910,7 +910,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 


		for_each_dsi_port(port, intel_dsi->ports) {

			dsi_trans = dsi_port_to_transcoder(port);

			intel_de_write(dev_priv, HSYNC(dsi_trans),

			intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),

				       (hsync_start - 1) | ((hsync_end - 1) << 16));

		}

	}
@@ -924,7 +924,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
		 * struct drm_display_mode.

		 * For interlace mode: program required pixel minus 2

		 */

		intel_de_write(dev_priv, VTOTAL(dsi_trans),

		intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),

			       (vactive - 1) | ((vtotal - 1) << 16));

	}
@@ -938,7 +938,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	if (is_vid_mode(intel_dsi)) {

		for_each_dsi_port(port, intel_dsi->ports) {

			dsi_trans = dsi_port_to_transcoder(port);

			intel_de_write(dev_priv, VSYNC(dsi_trans),

			intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),

				       (vsync_start - 1) | ((vsync_end - 1) << 16));

		}

	}
@@ -952,7 +952,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	if (is_vid_mode(intel_dsi)) {

		for_each_dsi_port(port, intel_dsi->ports) {

			dsi_trans = dsi_port_to_transcoder(port);

			intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans),

			intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans),

				       vsync_shift);

		}

	}
@@ -961,7 +961,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	if (DISPLAY_VER(dev_priv) >= 12) {

		for_each_dsi_port(port, intel_dsi->ports) {

			dsi_trans = dsi_port_to_transcoder(port);

			intel_de_write(dev_priv, VBLANK(dsi_trans),

			intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),

				       (vactive - 1) | ((vtotal - 1) << 16));

		}

	}

drivers/gpu/drm/i915/display/intel_crt.c

+10 −9
Original line number Diff line number Diff line
@@ -678,10 +678,11 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) 
}



static enum drm_connector_status

intel_crt_load_detect(struct intel_crt *crt, u32 pipe)

intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)

{

	struct drm_device *dev = crt->base.base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	enum transcoder cpu_transcoder = (enum transcoder)pipe;

	u32 save_bclrpat;

	u32 save_vtotal;

	u32 vtotal, vactive;
@@ -693,9 +694,9 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 


	drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");



	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(pipe));

	save_vtotal = intel_de_read(dev_priv, VTOTAL(pipe));

	vblank = intel_de_read(dev_priv, VBLANK(pipe));

	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));

	save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));

	vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));



	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;

	vactive = (save_vtotal & 0x7ff) + 1;
@@ -704,7 +705,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 
	vblank_end = ((vblank >> 16) & 0xfff) + 1;



	/* Set the border color to purple. */

	intel_de_write(dev_priv, BCLRPAT(pipe), 0x500050);

	intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);



	if (DISPLAY_VER(dev_priv) != 2) {

		u32 pipeconf = intel_de_read(dev_priv, PIPECONF(pipe));
@@ -730,11 +731,11 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 
		* Yes, this will flicker

		*/

		if (vblank_start <= vactive && vblank_end >= vtotal) {

			u32 vsync = intel_de_read(dev_priv, VSYNC(pipe));

			u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));

			u32 vsync_start = (vsync & 0xffff) + 1;



			vblank_start = vsync_start;

			intel_de_write(dev_priv, VBLANK(pipe),

			intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),

				       (vblank_start - 1) | ((vblank_end - 1) << 16));

			restore_vblank = true;

		}
@@ -766,7 +767,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 


		/* restore vblank if necessary */

		if (restore_vblank)

			intel_de_write(dev_priv, VBLANK(pipe), vblank);

			intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);

		/*

		 * If more than 3/4 of the scanline detected a monitor,

		 * then it is assumed to be present. This works even on i830,
@@ -779,7 +780,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 
	}



	/* Restore previous settings */

	intel_de_write(dev_priv, BCLRPAT(pipe), save_bclrpat);

	intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);



	return status;

}

drivers/gpu/drm/i915/display/intel_display.c

+25 −24
Original line number Diff line number Diff line
@@ -1751,7 +1751,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta 
	intel_set_transcoder_timings(crtc_state);



	if (cpu_transcoder != TRANSCODER_EDP)

		intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),

		intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),

			       crtc_state->pixel_multiplier - 1);



	hsw_set_frame_start_delay(crtc_state);
@@ -2747,21 +2747,21 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta 
	}



	if (DISPLAY_VER(dev_priv) > 3)

		intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),

		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),

			       vsyncshift);



	intel_de_write(dev_priv, HTOTAL(cpu_transcoder),

	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),

		       (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));

	intel_de_write(dev_priv, HBLANK(cpu_transcoder),

	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),

		       (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));

	intel_de_write(dev_priv, HSYNC(cpu_transcoder),

	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),

		       (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));



	intel_de_write(dev_priv, VTOTAL(cpu_transcoder),

	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),

		       (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));

	intel_de_write(dev_priv, VBLANK(cpu_transcoder),

	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),

		       (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));

	intel_de_write(dev_priv, VSYNC(cpu_transcoder),

	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),

		       (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));



	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
@@ -2770,8 +2770,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta 
	 * bits. */

	if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&

	    (pipe == PIPE_B || pipe == PIPE_C))

		intel_de_write(dev_priv, VTOTAL(pipe),

		               intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));

		intel_de_write(dev_priv, TRANS_VTOTAL(pipe),

			       intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));



}
@@ -2813,33 +2813,33 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, 
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;

	u32 tmp;



	tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));

	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));

	pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;

	pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;



	if (!transcoder_is_dsi(cpu_transcoder)) {

		tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));

		tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));

		pipe_config->hw.adjusted_mode.crtc_hblank_start =

							(tmp & 0xffff) + 1;

		pipe_config->hw.adjusted_mode.crtc_hblank_end =

						((tmp >> 16) & 0xffff) + 1;

	}

	tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));

	tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));

	pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;

	pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;



	tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));

	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));

	pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;

	pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;



	if (!transcoder_is_dsi(cpu_transcoder)) {

		tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));

		tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));

		pipe_config->hw.adjusted_mode.crtc_vblank_start =

							(tmp & 0xffff) + 1;

		pipe_config->hw.adjusted_mode.crtc_vblank_end =

						((tmp >> 16) & 0xffff) + 1;

	}

	tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));

	tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));

	pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;

	pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
@@ -3995,7 +3995,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, 
	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {

		pipe_config->pixel_multiplier =

			intel_de_read(dev_priv,

				      PIPE_MULT(pipe_config->cpu_transcoder)) + 1;

				      TRANS_MULT(pipe_config->cpu_transcoder)) + 1;

	} else {

		pipe_config->pixel_multiplier = 1;

	}
@@ -8601,6 +8601,7 @@ int intel_modeset_init(struct drm_i915_private *i915) 
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)

{

	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);

	enum transcoder cpu_transcoder = (enum transcoder)pipe;

	/* 640x480@60Hz, ~25175 kHz */

	struct dpll clock = {

		.m1 = 18,
@@ -8627,12 +8628,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 
		PLL_REF_INPUT_DREFCLK |

		DPLL_VCO_ENABLE;



	intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));

	intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));

	intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));

	intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));

	intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));

	intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));

	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));

	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));

	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), (656 - 1) | ((752 - 1) << 16));

	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));

	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));

	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), (490 - 1) | ((492 - 1) << 16));

	intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));



	intel_de_write(dev_priv, FP0(pipe), fp);

drivers/gpu/drm/i915/display/intel_pch_display.c

+7 −7
Original line number Diff line number Diff line
@@ -220,20 +220,20 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s 
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;



	intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),

		       intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));

		       intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)));

	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),

		       intel_de_read(dev_priv, HBLANK(cpu_transcoder)));

		       intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));

	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),

		       intel_de_read(dev_priv, HSYNC(cpu_transcoder)));

		       intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));



	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),

		       intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));

		       intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));

	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),

		       intel_de_read(dev_priv, VBLANK(cpu_transcoder)));

		       intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));

	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),

		       intel_de_read(dev_priv, VSYNC(cpu_transcoder)));

		       intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));

	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),

		       intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));

		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));

}



static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

+2 −2
Original line number Diff line number Diff line
@@ -1041,7 +1041,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, 
	}



	if (DISPLAY_VER(dev_priv) >= 12) {

		val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));

		val = intel_de_read(dev_priv, TRANS_EXITLINE(intel_dp->psr.transcoder));

		val &= EXITLINE_MASK;

		pipe_config->dc3co_exitline = val;

	}
@@ -1120,7 +1120,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, 
	 * transcoder, EXITLINE will need to be unset when disabling PSR

	 */

	if (intel_dp->psr.dc3co_exitline)

		intel_de_rmw(dev_priv, EXITLINE(cpu_transcoder), EXITLINE_MASK,

		intel_de_rmw(dev_priv, TRANS_EXITLINE(cpu_transcoder), EXITLINE_MASK,

			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);



	if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))