Commit 5ab37851 authored by Weili Qian's avatar Weili Qian Committed by JiangShui
Browse files

crypto: hisilicon/hpre - mask cluster timeout error 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I8LFYK


CVE: NA

----------------------------------------------------------------------

The maximum timeout of the hpre cluster is 16 ms.
When a page fault occurs, the CPU core may process the
page fault event longer than 16 ms, especially when
the guest OS processes the page fault event reported
by the SMMU.

In the current test, there is a high probability that the
cluster times out. However, the cluster is waiting for the
completion of memory access, which is not an error. Therefore,
the device does not need to be reset. If an error occurs in the
cluster, the QM also reports the error. Therefore, the cluster
timeout error of hpre can be masked.

Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
parent 7ab780f8

drivers/crypto/hisilicon/hpre/hpre_main.c

+6 −16
Original line number Diff line number Diff line
@@ -13,9 +13,7 @@ 
#include <linux/topology.h>

#include "hpre.h"



#define HPRE_QM_ABNML_INT_MASK		0x100004

#define HPRE_CTRL_CNT_CLR_CE_BIT	BIT(0)

#define HPRE_COMM_CNT_CLR_CE		0x0

#define HPRE_CTRL_CNT_CLR_CE		0x301000

#define HPRE_FSM_MAX_CNT		0x301008

#define HPRE_VFG_AXQOS			0x30100c
@@ -42,7 +40,6 @@ 
#define HPRE_HAC_INT_SET		0x301500

#define HPRE_RNG_TIMEOUT_NUM		0x301A34

#define HPRE_CORE_INT_ENABLE		0

#define HPRE_CORE_INT_DISABLE		GENMASK(21, 0)

#define HPRE_RDCHN_INI_ST		0x301a00

#define HPRE_CLSTR_BASE			0x302000

#define HPRE_CORE_EN_OFFSET		0x04
@@ -66,7 +63,6 @@ 
#define HPRE_CLSTR_ADDR_INTRVL		0x1000

#define HPRE_CLUSTER_INQURY		0x100

#define HPRE_CLSTR_ADDR_INQRY_RSLT	0x104

#define HPRE_TIMEOUT_ABNML_BIT		6

#define HPRE_PASID_EN_BIT		9

#define HPRE_REG_RD_INTVRL_US		10

#define HPRE_REG_RD_TMOUT_US		1000
@@ -203,9 +199,9 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { 
	{HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},

	{HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},

	{HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},

	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFFFE},

	{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE},

	{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE},

	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFC3E},

	{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFC3E},

	{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFC3E},

	{HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},

	{HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0,  0x4, 0x1},

	{HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},
@@ -656,11 +652,6 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 
	writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);

	writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);



	/* HPRE need more time, we close this interrupt */

	val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK);

	val |= BIT(HPRE_TIMEOUT_ABNML_BIT);

	writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK);



	if (qm->ver >= QM_HW_V3)

		writel(HPRE_RSA_ENB | HPRE_ECC_ENB,

			qm->io_base + HPRE_TYPES_ENB);
@@ -669,9 +660,7 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 


	writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);

	writel(0x0, qm->io_base + HPRE_BD_ENDIAN);

	writel(0x0, qm->io_base + HPRE_INT_MASK);

	writel(0x0, qm->io_base + HPRE_POISON_BYPASS);

	writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE);

	writel(0x0, qm->io_base + HPRE_ECC_BYPASS);



	writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);
@@ -761,7 +750,7 @@ static void hpre_hw_error_disable(struct hisi_qm *qm) 


static void hpre_hw_error_enable(struct hisi_qm *qm)

{

	u32 ce, nfe;

	u32 ce, nfe, err_en;



	ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);

	nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
@@ -778,7 +767,8 @@ static void hpre_hw_error_enable(struct hisi_qm *qm) 
	hpre_master_ooo_ctrl(qm, true);



	/* enable hpre hw error interrupts */

	writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK);

	err_en = ce | nfe | HPRE_HAC_RAS_FE_ENABLE;

	writel(~err_en, qm->io_base + HPRE_INT_MASK);

}



static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file)