Commit 5aafda60 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

arm64: dts: imx8mn-evk: Add camera support 



Add support for the OV5640 camera.

Tested with the following commands:

media-ctl -l "'ov5640 2-003c':0 -> 'csis-32e30000.mipi-csi':0 [1]"
media-ctl -V "'ov5640 2-003c':0 [fmt:UYVY8_1X16/640x480 field:none]"
media-ctl -V "'crossbar':0 [fmt:UYVY8_1X16/640x480 field:none]"
media-ctl -V "'mxc_isi.0':0 [fmt:UYVY8_1X16/640x480 field:none]"
v4l2-ctl --device /dev/video0 --set-fmt-video=width=640,height=480,pixelformat=YUYV
v4l2-ctl --stream-mmap -d /dev/video0;
gst-launch-1.0 -v v4l2src device=/dev/video0 ! video/x-raw,width=640,height=480 ! waylandsink

Signed-off-by: default avatarFabio Estevam <festevam@denx.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e8abdd58

arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -259,6 +259,45 @@ 
		gpio-controller;

		#gpio-cells = <2>;

	};



	camera@3c {

		compatible = "ovti,ov5640";

		reg = <0x3c>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_camera>;

		clocks = <&clk IMX8MN_CLK_CLKO1>;

		clock-names = "xclk";

		assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;

		assigned-clock-parents = <&clk IMX8MN_CLK_24M>;

		assigned-clock-rates = <24000000>;

		powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;

		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;



		port {

			ov5640_to_mipi_csi2: endpoint {

				remote-endpoint = <&imx8mn_mipi_csi_in>;

				clock-lanes = <0>;

				data-lanes = <1 2>;

			};

		};

	};

};



&isi {

	status = "okay";

};



&mipi_csi {

	status = "okay";



	ports {

		port@0 {

			imx8mn_mipi_csi_in: endpoint {

				remote-endpoint = <&ov5640_to_mipi_csi2>;

				data-lanes = <1 2>;

			};

		};

	};

};



&lcdif {
@@ -393,6 +432,14 @@ 
};



&iomuxc {

	pinctrl_camera: cameragrp {

		fsl,pins = <

			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19

			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19

			MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59

		>;

	};



	pinctrl_fec1: fec1grp {

		fsl,pins = <

			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3