Unverified Commit 5a6694b0 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!7067 crypto: hisilicon fix some issues 

Merge Pull Request from: @xiao_jiang_shui 
 
crypto: hisilicon/zip - optimize the address offset of the reg query function
crypto: hisilicon/qm - adjust the internal processing sequence of the vf enable and disable
uacce: fix for cdev memory leak

issue: https://gitee.com/openeuler/kernel/issues/I9NUTY 
 
Link:https://gitee.com/openeuler/kernel/pulls/7067

 

Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
parents 34397912 3cf71ab1

drivers/crypto/hisilicon/qm.c

+1 −6
Original line number Diff line number Diff line
@@ -3953,7 +3953,6 @@ EXPORT_SYMBOL_GPL(hisi_qm_sriov_enable); 
int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen)

{

	struct hisi_qm *qm = pci_get_drvdata(pdev);

	int ret;



	if (pci_vfs_assigned(pdev)) {

		pci_err(pdev, "Failed to disable VFs as VFs are assigned!\n");
@@ -3968,13 +3967,9 @@ int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen) 


	pci_disable_sriov(pdev);



	ret = qm_clear_vft_config(qm);

	if (ret)

		return ret;



	qm_pm_put_sync(qm);



	return 0;

	return qm_clear_vft_config(qm);

}

EXPORT_SYMBOL_GPL(hisi_qm_sriov_disable);

drivers/crypto/hisilicon/zip/zip_main.c

+20 −28
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
#define HZIP_QM_IDEL_STATUS		0x3040e4



#define HZIP_CORE_DFX_BASE		0x301000

#define HZIP_CLOCK_GATED_CONTL		0X301004

#define HZIP_CORE_DFX_DECOMP_BASE	0x304000

#define HZIP_CORE_DFX_COMP_0		0x302000

#define HZIP_CORE_DFX_COMP_1		0x303000

#define HZIP_CORE_DFX_DECOMP_0		0x304000
@@ -47,6 +47,7 @@ 
#define HZIP_CORE_DFX_DECOMP_5		0x309000

#define HZIP_CORE_REGS_BASE_LEN		0xB0

#define HZIP_CORE_REGS_DFX_LEN		0x28

#define HZIP_CORE_ADDR_INTRVL		0X1000



#define HZIP_CORE_INT_SOURCE		0x3010A0

#define HZIP_CORE_INT_MASK_REG		0x3010A4
@@ -268,28 +269,6 @@ static const u32 zip_pre_store_caps[] = { 
	ZIP_DEV_ALG_BITMAP,

};



enum {

	HZIP_COMP_CORE0,

	HZIP_COMP_CORE1,

	HZIP_DECOMP_CORE0,

	HZIP_DECOMP_CORE1,

	HZIP_DECOMP_CORE2,

	HZIP_DECOMP_CORE3,

	HZIP_DECOMP_CORE4,

	HZIP_DECOMP_CORE5,

};



static const u64 core_offsets[] = {

	[HZIP_COMP_CORE0]   = 0x302000,

	[HZIP_COMP_CORE1]   = 0x303000,

	[HZIP_DECOMP_CORE0] = 0x304000,

	[HZIP_DECOMP_CORE1] = 0x305000,

	[HZIP_DECOMP_CORE2] = 0x306000,

	[HZIP_DECOMP_CORE3] = 0x307000,

	[HZIP_DECOMP_CORE4] = 0x308000,

	[HZIP_DECOMP_CORE5] = 0x309000,

};



static const struct debugfs_reg32 hzip_dfx_regs[] = {

	{"HZIP_GET_BD_NUM                ",  0x00},

	{"HZIP_GET_RIGHT_BD              ",  0x04},
@@ -806,6 +785,18 @@ static int hisi_zip_regs_show(struct seq_file *s, void *unused) 


DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs);



static void __iomem *get_zip_core_addr(struct hisi_qm *qm, int core_num)

{

	u32 zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;



	if (core_num < zip_comp_core_num)

		return qm->io_base + HZIP_CORE_DFX_BASE +

			(core_num + 1) * HZIP_CORE_ADDR_INTRVL;

	else

		return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE +

			(core_num - zip_comp_core_num) * HZIP_CORE_ADDR_INTRVL;

}



static int hisi_zip_core_debug_init(struct hisi_qm *qm)

{

	u32 zip_core_num, zip_comp_core_num;
@@ -831,7 +822,7 @@ static int hisi_zip_core_debug_init(struct hisi_qm *qm) 


		regset->regs = hzip_dfx_regs;

		regset->nregs = ARRAY_SIZE(hzip_dfx_regs);

		regset->base = qm->io_base + core_offsets[i];

		regset->base = get_zip_core_addr(qm, i);

		regset->dev = dev;



		tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
@@ -920,13 +911,14 @@ static int hisi_zip_debugfs_init(struct hisi_qm *qm) 
/* hisi_zip_debug_regs_clear() - clear the zip debug regs */

static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)

{

	u32 zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;

	int i, j;



	/* enable register read_clear bit */

	writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);

	for (i = 0; i < ARRAY_SIZE(core_offsets); i++)

	for (i = 0; i < zip_core_num; i++)

		for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++)

			readl(qm->io_base + core_offsets[i] +

			readl(get_zip_core_addr(qm, i) +

			      hzip_dfx_regs[j].offset);



	/* disable register read_clear bit */
@@ -969,7 +961,7 @@ static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 
	}



	for (i = 0; i < zip_core_num; i++) {

		io_base = qm->io_base + core_offsets[i];

		io_base = get_zip_core_addr(qm, i);

		for (j = 0; j < core_dfx_regs_num; j++) {

			idx = com_dfx_regs_num + i * core_dfx_regs_num + j;

			debug->last_words[idx] = readl_relaxed(
@@ -1021,7 +1013,7 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 
		else

			scnprintf(buf, sizeof(buf), "Decomp_core-%d",

				  i - zip_comp_core_num);

		base = qm->io_base + core_offsets[i];

		base = get_zip_core_addr(qm, i);



		pci_info(qm->pdev, "==>%s:\n", buf);

		/* dump last word for dfx regs during control resetting */

drivers/misc/uacce/uacce.c

+10 −1
Original line number Diff line number Diff line
@@ -984,6 +984,8 @@ EXPORT_SYMBOL_GPL(uacce_alloc); 
 */

int uacce_register(struct uacce_device *uacce)

{

	int ret;



	if (!uacce)

		return -ENODEV;
@@ -994,7 +996,14 @@ int uacce_register(struct uacce_device *uacce) 
	uacce->cdev->ops = &uacce_fops;

	uacce->cdev->owner = THIS_MODULE;



	return cdev_device_add(uacce->cdev, &uacce->dev);

	ret = cdev_device_add(uacce->cdev, &uacce->dev);

	if (ret) {

		cdev_del(uacce->cdev);

		uacce->cdev = NULL;

		return ret;

	}



	return 0;

}

EXPORT_SYMBOL_GPL(uacce_register);