Commit 5a645ff5 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdgpu: Correctly clear GCEA error status 



While clearing GCEA error status, do not clear the bits
set by RAS TA.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: default avatarJohn Clements <john.clements@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e8ce3d47

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

+7 −3
Original line number Diff line number Diff line
@@ -1676,13 +1676,14 @@ static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev) 
	uint32_t i, j;

	uint32_t value;



	value = REG_SET_FIELD(0, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);



	mutex_lock(&adev->grbm_idx_mutex);

	for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {

		for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;

		     j++) {

			gfx_v9_4_2_select_se_sh(adev, i, 0, j);

			value = RREG32(SOC15_REG_ENTRY_OFFSET(

				gfx_v9_4_2_ea_err_status_regs));

			value = REG_SET_FIELD(value, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);

			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value);

		}

	}
@@ -1734,6 +1735,7 @@ static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev) 
			gfx_v9_4_2_select_se_sh(adev, i, 0, j);

			reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

				gfx_v9_4_2_ea_err_status_regs));



			if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||

			    REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||

			    REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
@@ -1741,7 +1743,9 @@ static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev) 
						j, reg_value);

			}

			/* clear after read */

			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10);

			reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,

						  CLEAR_ERROR_STATUS, 0x1);

			WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), reg_value);

		}

	}