Commit 5a487cf7 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'misc-habanalabs-next-2020-09-25' of... 

Merge tag 'misc-habanalabs-next-2020-09-25' of git://people.freedesktop.org/~gabbayo/linux into char-misc-next

Oded writes:

This tag contains the following changes for kernel 5.10-rc1:

- release the kernel context object after we reset the device. This is
  needed to prevent a race where the firmware still has some in-flight
  transcations that require the kernel context (and its memory mappings) to
  be alive.

- replace constant numbers with defines in QMAN initialization of GAUDI

- correct an error message text and add a few debug messages to help debug
  issues that happen during context open and close.

* tag 'misc-habanalabs-next-2020-09-25' of git://people.freedesktop.org/~gabbayo/linux:
  habanalabs/gaudi: configure QMAN LDMA registers properly
  habanalabs: add notice of device not idle
  habanalabs: add debug messages for opening/closing context
  habanalabs: release kernel context after hw_fini
  habanalabs: correct an error message
parents 9eb29f2e 25121d98

drivers/misc/habanalabs/common/context.c

+13 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
static void hl_ctx_fini(struct hl_ctx *ctx)

{

	struct hl_device *hdev = ctx->hdev;

	u64 idle_mask = 0;

	int i;



	/*
@@ -28,6 +29,8 @@ static void hl_ctx_fini(struct hl_ctx *ctx) 
	kfree(ctx->cs_pending);



	if (ctx->asid != HL_KERNEL_ASID_ID) {

		dev_dbg(hdev->dev, "closing user context %d\n", ctx->asid);



		/* The engines are stopped as there is no executing CS, but the

		 * Coresight might be still working by accessing addresses

		 * related to the stopped engines. Hence stop it explicitly.
@@ -40,7 +43,15 @@ static void hl_ctx_fini(struct hl_ctx *ctx) 
		hl_cb_va_pool_fini(ctx);

		hl_vm_ctx_fini(ctx);

		hl_asid_free(hdev, ctx->asid);



		if ((!hdev->pldm) && (hdev->pdev) &&

				(!hdev->asic_funcs->is_device_idle(hdev,

							&idle_mask, NULL)))

			dev_notice(hdev->dev,

				"device not idle after user context is closed (0x%llx)\n",

				idle_mask);

	} else {

		dev_dbg(hdev->dev, "closing kernel context\n");

		hl_mmu_ctx_fini(ctx);

	}

}
@@ -168,6 +179,8 @@ int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx) 
			dev_err(hdev->dev, "ctx_init failed\n");

			goto err_cb_va_pool_fini;

		}



		dev_dbg(hdev->dev, "create user context %d\n", ctx->asid);

	}



	return 0;

drivers/misc/habanalabs/common/device.c

+6 −7
Original line number Diff line number Diff line
@@ -967,14 +967,13 @@ int hl_device_reset(struct hl_device *hdev, bool hard_reset, 
		flush_workqueue(hdev->eq_wq);

	}



	/* Release kernel context */

	if ((hard_reset) && (hl_ctx_put(hdev->kernel_ctx) == 1))

		hdev->kernel_ctx = NULL;



	/* Reset the H/W. It will be in idle state after this returns */

	hdev->asic_funcs->hw_fini(hdev, hard_reset);



	if (hard_reset) {

		/* Release kernel context */

		if (hl_ctx_put(hdev->kernel_ctx) == 1)

			hdev->kernel_ctx = NULL;

		hl_vm_fini(hdev);

		hl_mmu_fini(hdev);

		hl_eq_reset(hdev, &hdev->event_queue);
@@ -1465,13 +1464,13 @@ void hl_device_fini(struct hl_device *hdev) 


	hl_cb_pool_fini(hdev);



	/* Reset the H/W. It will be in idle state after this returns */

	hdev->asic_funcs->hw_fini(hdev, true);



	/* Release kernel context */

	if ((hdev->kernel_ctx) && (hl_ctx_put(hdev->kernel_ctx) != 1))

		dev_err(hdev->dev, "kernel ctx is still alive\n");



	/* Reset the H/W. It will be in idle state after this returns */

	hdev->asic_funcs->hw_fini(hdev, true);



	hl_vm_fini(hdev);



	hl_mmu_fini(hdev);

drivers/misc/habanalabs/common/memory.c

+2 −2
Original line number Diff line number Diff line
@@ -77,8 +77,8 @@ static int alloc_device_memory(struct hl_ctx *ctx, struct hl_mem_in *args, 
		paddr = (u64) gen_pool_alloc(vm->dram_pg_pool, total_size);

		if (!paddr) {

			dev_err(hdev->dev,

				"failed to allocate %llu huge contiguous pages\n",

				num_pgs);

				"failed to allocate %llu contiguous pages with total size of %llu\n",

				num_pgs, total_size);

			return -ENOMEM;

		}

	}

drivers/misc/habanalabs/gaudi/gaudi.c

+41 −21
Original line number Diff line number Diff line
@@ -1865,9 +1865,11 @@ static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id, 
	WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);

	WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);



	WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74);

	WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14);

	WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C);

	WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, QMAN_LDMA_SIZE_OFFSET);

	WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_SRC_OFFSET);

	WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_DST_OFFSET);



	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);

	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
@@ -2025,13 +2027,19 @@ static void gaudi_init_hbm_dma_qman(struct hl_device *hdev, int dma_id, 
		WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);

		WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);



		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC);

		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4);

		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C);

		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,

							QMAN_CPDMA_SIZE_OFFSET);

		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,

							QMAN_CPDMA_SRC_OFFSET);

		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,

							QMAN_CPDMA_DST_OFFSET);

	} else {

		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74);

		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14);

		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C);

		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,

							QMAN_LDMA_SIZE_OFFSET);

		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_SRC_OFFSET);

		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_SIZE_OFFSET);



		/* Configure RAZWI IRQ */

		dma_qm_err_cfg = HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
@@ -2135,13 +2143,19 @@ static void gaudi_init_mme_qman(struct hl_device *hdev, u32 mme_offset, 
		WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0);

		WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0);



		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC);

		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4);

		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C);

		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,

							QMAN_CPDMA_SIZE_OFFSET);

		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,

							QMAN_CPDMA_SRC_OFFSET);

		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,

							QMAN_CPDMA_DST_OFFSET);

	} else {

		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74);

		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14);

		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C);

		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,

							QMAN_LDMA_SIZE_OFFSET);

		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_SRC_OFFSET);

		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_DST_OFFSET);



		/* Configure RAZWI IRQ */

		mme_id = mme_offset /
@@ -2249,13 +2263,19 @@ static void gaudi_init_tpc_qman(struct hl_device *hdev, u32 tpc_offset, 
		WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0);

		WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0);



		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC);

		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4);

		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C);

		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,

							QMAN_CPDMA_SIZE_OFFSET);

		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,

							QMAN_CPDMA_SRC_OFFSET);

		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,

							QMAN_CPDMA_DST_OFFSET);

	} else {

		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74);

		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14);

		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C);

		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,

							QMAN_LDMA_SIZE_OFFSET);

		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_SRC_OFFSET);

		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,

							QMAN_LDMA_DST_OFFSET);



		/* Configure RAZWI IRQ */

		tpc_id = tpc_offset /

drivers/misc/habanalabs/gaudi/gaudiP.h

+8 −0
Original line number Diff line number Diff line
@@ -84,6 +84,14 @@ 


#define DMA_CORE_OFFSET		(mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)



#define QMAN_LDMA_SRC_OFFSET	(mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)

#define QMAN_LDMA_DST_OFFSET	(mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)

#define QMAN_LDMA_SIZE_OFFSET	(mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)



#define QMAN_CPDMA_SRC_OFFSET	(mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)

#define QMAN_CPDMA_DST_OFFSET	(mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)

#define QMAN_CPDMA_SIZE_OFFSET	(mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)



#define SIF_RTR_CTRL_OFFSET	(mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)



#define NIF_RTR_CTRL_OFFSET	(mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)