Commit 5a3ccb14 authored by Gabe Teeger's avatar Gabe Teeger Committed by Alex Deucher
Browse files

drm/amd/display: Remove wait while locked 



[Why]
We wait for mpc idle while in a locked state, leading to potential
deadlock.

[What]
Move the wait_for_idle call to outside of HW lock. This and a
call to wait_drr_doublebuffer_pending_clear are moved added to a new
static helper function called wait_for_outstanding_hw_updates, to make
the interface clearer.

Cc: stable@vger.kernel.org
Fixes: 8f0d304d ("drm/amd/display: Do not commit pipe when updating DRR")
Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarGabe Teeger <gabe.teeger@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1482650b

drivers/gpu/drm/amd/display/dc/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -78,3 +78,4 @@ DC_EDID += dc_edid_parser.o 
AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))

AMD_DISPLAY_EDID = $(addprefix $(AMDDALPATH)/dc/,$(DC_EDID))

AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB) $(AMD_DISPLAY_EDID)

drivers/gpu/drm/amd/display/dc/core/dc.c

+41 −17
Original line number Diff line number Diff line
@@ -3501,6 +3501,45 @@ static void commit_planes_for_stream_fast(struct dc *dc, 
		top_pipe_to_program->stream->update_flags.raw = 0;

}



static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state *dc_context)

{

/*

 * This function calls HWSS to wait for any potentially double buffered

 * operations to complete. It should be invoked as a pre-amble prior

 * to full update programming before asserting any HW locks.

 */

	int pipe_idx;

	int opp_inst;

	int opp_count = dc->res_pool->pipe_count;

	struct hubp *hubp;

	int mpcc_inst;

	const struct pipe_ctx *pipe_ctx;



	for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

		pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];



		if (!pipe_ctx->stream)

			continue;



		if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)

			pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);



		hubp = pipe_ctx->plane_res.hubp;

		if (!hubp)

			continue;



		mpcc_inst = hubp->inst;

		// MPCC inst is equal to pipe index in practice

		for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {

			if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {

				dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);

				dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;

				break;

			}

		}

	}

}



static void commit_planes_for_stream(struct dc *dc,

		struct dc_surface_update *srf_updates,

		int surface_count,
@@ -3519,24 +3558,9 @@ static void commit_planes_for_stream(struct dc *dc, 
	// dc->current_state anymore, so we have to cache it before we apply

	// the new SubVP context

	subvp_prev_use = false;





	dc_z10_restore(dc);



	if (update_type == UPDATE_TYPE_FULL) {

		/* wait for all double-buffer activity to clear on all pipes */

		int pipe_idx;



		for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {

			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];



			if (!pipe_ctx->stream)

				continue;



			if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)

				pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);

		}

	}

	if (update_type == UPDATE_TYPE_FULL)

		wait_for_outstanding_hw_updates(dc, context);



	if (update_type == UPDATE_TYPE_FULL) {

		dc_allow_idle_optimizations(dc, false);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+0 −11
Original line number Diff line number Diff line
@@ -1561,17 +1561,6 @@ static void dcn20_update_dchubp_dpp( 
			|| plane_state->update_flags.bits.global_alpha_change

			|| plane_state->update_flags.bits.per_pixel_alpha_change) {

		// MPCC inst is equal to pipe index in practice

		int mpcc_inst = hubp->inst;

		int opp_inst;

		int opp_count = dc->res_pool->pipe_count;



		for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {

			if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {

				dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);

				dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;

				break;

			}

		}

		hws->funcs.update_mpcc(dc, pipe_ctx);

	}