Commit 5a3c46b8 authored by Chaitanya Kumar Borah's avatar Chaitanya Kumar Borah Committed by Matt Roper
Browse files

drm/i915/display: Set correct voltage level for 480MHz CDCLK 



According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.

BSpec: 49208

Fixes: 06f1b06d ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")

v2: rebase

Signed-off-by: default avatarChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230529060747.3972259-1-chaitanya.kumar.borah@intel.com
parent f917130f

drivers/gpu/drm/i915/display/intel_cdclk.c

+26 −4
Original line number Diff line number Diff line
@@ -1453,6 +1453,18 @@ static u8 tgl_calc_voltage_level(int cdclk) 
		return 0;

}



static u8 rplu_calc_voltage_level(int cdclk)

{

	if (cdclk > 556800)

		return 3;

	else if (cdclk > 480000)

		return 2;

	else if (cdclk > 312000)

		return 1;

	else

		return 0;

}



static void icl_readout_refclk(struct drm_i915_private *dev_priv,

			       struct intel_cdclk_config *cdclk_config)

{
@@ -3397,6 +3409,13 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = { 
	.calc_voltage_level = tgl_calc_voltage_level,

};



static const struct intel_cdclk_funcs rplu_cdclk_funcs = {

	.get_cdclk = bxt_get_cdclk,

	.set_cdclk = bxt_set_cdclk,

	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,

	.calc_voltage_level = rplu_calc_voltage_level,

};



static const struct intel_cdclk_funcs tgl_cdclk_funcs = {

	.get_cdclk = bxt_get_cdclk,

	.set_cdclk = bxt_set_cdclk,
@@ -3539,14 +3558,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		dev_priv->display.cdclk.table = dg2_cdclk_table;

	} else if (IS_ALDERLAKE_P(dev_priv)) {

		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		/* Wa_22011320316:adl-p[a0] */

		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

			dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;

		else if (IS_ADLP_RPLU(dev_priv))

			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		} else if (IS_ADLP_RPLU(dev_priv)) {

			dev_priv->display.cdclk.table = rplu_cdclk_table;

		else

			dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;

		} else {

			dev_priv->display.cdclk.table = adlp_cdclk_table;

			dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		}

	} else if (IS_ROCKETLAKE(dev_priv)) {

		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		dev_priv->display.cdclk.table = rkl_cdclk_table;