Commit 5a2730fc authored by Fangzhi Zuo's avatar Fangzhi Zuo Committed by Alex Deucher
Browse files

drm/amd/display: Add DP 2.0 BIOS and DMUB Support 



Parse DP2 encoder caps and hpo instance from bios

Signed-off-by: default avatarFangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d76b12da

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+10 −0
Original line number Diff line number Diff line
@@ -1604,6 +1604,16 @@ static enum bp_result bios_parser_get_encoder_cap_info( 
			ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;

	info->HDMI_6GB_EN = (record->encodercaps &

			ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;

#if defined(CONFIG_DRM_AMD_DC_DCN)

	info->IS_DP2_CAPABLE = (record->encodercaps &

			ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;

	info->DP_UHBR10_EN = (record->encodercaps &

			ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;

	info->DP_UHBR13_5_EN = (record->encodercaps &

			ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;

	info->DP_UHBR20_EN = (record->encodercaps &

			ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;

#endif

	info->DP_IS_USB_C = (record->encodercaps &

			ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

+10 −0
Original line number Diff line number Diff line
@@ -340,6 +340,13 @@ static enum bp_result transmitter_control_v1_7( 
	const struct command_table_helper *cmd = bp->cmd_helper;

	struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7 = {0};



#if defined(CONFIG_DRM_AMD_DC_DCN)

	uint8_t hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_0;



	if (dc_is_dp_signal(cntl->signal))

		hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_DP_0;

#endif



	dig_v1_7.phyid = cmd->phy_id_to_atom(cntl->transmitter);

	dig_v1_7.action = (uint8_t)cntl->action;
@@ -353,6 +360,9 @@ static enum bp_result transmitter_control_v1_7( 
	dig_v1_7.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);

	dig_v1_7.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);

	dig_v1_7.connobj_id = (uint8_t)cntl->connector_obj_id.id;

#if defined(CONFIG_DRM_AMD_DC_DCN)

	dig_v1_7.HPO_instance = hpo_instance;

#endif

	dig_v1_7.symclk_units.symclk_10khz = cntl->pixel_clock/10;



	if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c

+4 −0
Original line number Diff line number Diff line
@@ -192,6 +192,10 @@ void dcn30_link_encoder_construct( 
		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

				bp_cap_info.DP_HBR3_EN;

		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

		enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;

		enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;

		enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;

		enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;

		enc10->base.features.flags.bits.DP_IS_USB_C =

				bp_cap_info.DP_IS_USB_C;

	} else {

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

+4 −0
Original line number Diff line number Diff line
@@ -59,6 +59,10 @@ struct encoder_feature_support { 
			uint32_t IS_TPS3_CAPABLE:1;

			uint32_t IS_TPS4_CAPABLE:1;

			uint32_t HDMI_6GB_EN:1;

			uint32_t IS_DP2_CAPABLE:1;

			uint32_t IS_UHBR10_CAPABLE:1;

			uint32_t IS_UHBR13_5_CAPABLE:1;

			uint32_t IS_UHBR20_CAPABLE:1;

			uint32_t DP_IS_USB_C:1;

		} bits;

		uint32_t raw;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+1 −1
Original line number Diff line number Diff line
@@ -974,7 +974,7 @@ struct dmub_dig_transmitter_control_data_v1_7 { 
	uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */

	uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */

	uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */

	uint8_t reserved0; /**< For future use */

	uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */

	uint8_t reserved1; /**< For future use */

	uint8_t reserved2[3]; /**< For future use */

	uint32_t reserved3[11]; /**< For future use */