Commit 59ea2887 authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Jani Nikula
Browse files

drm/i915/display/misc: use intel_de_rmw if possible 



The helper makes the code more compact and readable.

Signed-off-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230110113656.4050491-1-andrzej.hajda@intel.com
parent 8910d8b7

drivers/gpu/drm/i915/display/g4x_dp.c

+4 −8
Original line number Diff line number Diff line
@@ -136,16 +136,12 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 


		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {

		u32 trans_dp;



		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;



		trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));

		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

			trans_dp |= TRANS_DP_ENH_FRAMING;

		else

			trans_dp &= ~TRANS_DP_ENH_FRAMING;

		intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);

		intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),

			     TRANS_DP_ENH_FRAMING,

			     drm_dp_enhanced_frame_cap(intel_dp->dpcd) ?

			     TRANS_DP_ENH_FRAMING : 0);

	} else {

		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)

			intel_dp->DP |= DP_COLOR_RANGE_16_235;

drivers/gpu/drm/i915/display/intel_drrs.c

+3 −9
Original line number Diff line number Diff line
@@ -68,21 +68,15 @@ intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc, 
{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum transcoder cpu_transcoder = crtc->drrs.cpu_transcoder;

	u32 val, bit;

	u32 bit;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		bit = PIPECONF_REFRESH_RATE_ALT_VLV;

	else

		bit = PIPECONF_REFRESH_RATE_ALT_ILK;



	val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));



	if (refresh_rate == DRRS_REFRESH_RATE_LOW)

		val |= bit;

	else

		val &= ~bit;



	intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);

	intel_de_rmw(dev_priv, PIPECONF(cpu_transcoder),

		     bit, refresh_rate == DRRS_REFRESH_RATE_LOW ? bit : 0);

}



static void

drivers/gpu/drm/i915/display/intel_dvo.c

+2 −5
Original line number Diff line number Diff line
@@ -444,11 +444,8 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv, 
	 * the clock enabled before we attempt to initialize

	 * the device.

	 */

	for_each_pipe(dev_priv, pipe) {

		dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe));

		intel_de_write(dev_priv, DPLL(pipe),

			       dpll[pipe] | DPLL_DVO_2X_MODE);

	}

	for_each_pipe(dev_priv, pipe)

		dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE);



	ret = dvo->dev_ops->init(&intel_dvo->dev, i2c);

drivers/gpu/drm/i915/display/intel_tv.c

+2 −4
Original line number Diff line number Diff line
@@ -930,8 +930,7 @@ intel_enable_tv(struct intel_atomic_state *state, 
	/* Prevents vblank waits from timing out in intel_tv_detect_type() */

	intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));



	intel_de_write(dev_priv, TV_CTL,

		       intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE);

	intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE);

}



static void
@@ -943,8 +942,7 @@ intel_disable_tv(struct intel_atomic_state *state, 
	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);



	intel_de_write(dev_priv, TV_CTL,

		       intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE);

	intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0);

}



static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)