Unverified Commit 59bb3d32 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!3219 crypto: hisiilicon some bugfixs and cleanup 

Merge Pull Request from: @xiao_jiang_shui 
 
Chenghai Huang (3):
  crypto: hisilicon/qm - delete a dbg function
  vfio/migration - delete a dbg function
  crypto: hisilicon/sec2 - optimize the error return process

JiangShui Yang (1):
  crypto: hisilicon/qm - increase the maximum waiting timeout interval
    of the moilbox.

Weili Qian (8):
  crypto: hisilicon/sec2: fix memory use-after-free issue
  crypto: hisilicon/qm - modify interrupt resource application process
  crypto: hisilicon/hpre - mask cluster timeout error
  crypto: hisilicon/qm - support get deivce state
  crypto: hisilicon/qm - dump important registers values before
    resetting
  crypto: hisilicon/qm - remove duplicate configurations
  crypto: hisilicon/qm - add stop function by hardware
  crypto: hisilicon/qm - reset device before enabling it

Wenkai Lin (1):
  crypto: hisilicon/qm - add size check in qm set algs

issue: https://gitee.com/openeuler/kernel/issues/I8LFYK 
 
Link:https://gitee.com/openeuler/kernel/pulls/3219

 

Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 67d516f9 1e00d1ae

Documentation/ABI/testing/debugfs-hisi-hpre

+7 −0
Original line number Diff line number Diff line
@@ -109,6 +109,13 @@ Description: Dump the stop queue status of the QM. The default value is 0, 
		will return non-zero value. Available for both PF and VF,

		and take no other effect on HPRE.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/qm/qm_state

Date:		Dec 2023

Contact:	qianweili@huawei.com

Description:	Dump the status of the device.

		0: busy, 1: idle.

		Only available for PF, and take no other effect on HPRE.



What:           /sys/kernel/debug/hisi_hpre/<bdf>/hpre_dfx/send_cnt

Date:           Apr 2020

Contact:        linux-crypto@vger.kernel.org

Documentation/ABI/testing/debugfs-hisi-sec

+7 −0
Original line number Diff line number Diff line
@@ -89,6 +89,13 @@ Description: Dump the stop queue status of the QM. The default value is 0, 
		will return non-zero value. Available for both PF and VF,

		and take no other effect on SEC.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_state

Date:		Dec 2023

Contact:	qianweili@huawei.com

Description:	Dump the status of the device.

		0: busy, 1: idle.

		Only available for PF, and take no other effect on SEC.



What:           /sys/kernel/debug/hisi_sec2/<bdf>/sec_dfx/send_cnt

Date:           Apr 2020

Contact:        linux-crypto@vger.kernel.org

Documentation/ABI/testing/debugfs-hisi-zip

+7 −0
Original line number Diff line number Diff line
@@ -102,6 +102,13 @@ Description: Dump the stop queue status of the QM. The default value is 0, 
		will return non-zero value. Available for both PF and VF,

		and take no other effect on ZIP.



What:		/sys/kernel/debug/hisi_zip/<bdf>/qm/qm_state

Date:		Dec 2023

Contact:	qianweili@huawei.com

Description:	Dump the status of the device.

		0: busy, 1: idle.

		Only available for PF, and take no other effect on ZIP.



What:           /sys/kernel/debug/hisi_zip/<bdf>/zip_dfx/send_cnt

Date:           Apr 2020

Contact:        linux-crypto@vger.kernel.org

drivers/crypto/hisilicon/debugfs.c

+53 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
#define QM_DFX_QN_SHIFT			16

#define QM_DFX_CNT_CLR_CE		0x100118

#define QM_DBG_WRITE_LEN		1024

#define QM_IN_IDLE_ST_REG		0x1040e4

#define QM_IN_IDLE_STATE		0x1



static const char * const qm_debug_file_name[] = {

	[CURRENT_QM]   = "current_qm",
@@ -81,6 +83,30 @@ static const struct debugfs_reg32 qm_dfx_regs[] = { 
	{"QM_DFX_FF_ST5                 ",  0x1040dc},

	{"QM_DFX_FF_ST6                 ",  0x1040e0},

	{"QM_IN_IDLE_ST                 ",  0x1040e4},

	{"QM_CACHE_CTL                  ",  0x100050},

	{"QM_TIMEOUT_CFG                ",  0x100070},

	{"QM_DB_TIMEOUT_CFG             ",  0x100074},

	{"QM_FLR_PENDING_TIME_CFG       ",  0x100078},

	{"QM_ARUSR_MCFG1                ",  0x100088},

	{"QM_AWUSR_MCFG1                ",  0x100098},

	{"QM_AXI_M_CFG_ENABLE           ",  0x1000B0},

	{"QM_RAS_CE_THRESHOLD           ",  0x1000F8},

	{"QM_AXI_TIMEOUT_CTRL           ",  0x100120},

	{"QM_AXI_TIMEOUT_STATUS         ",  0x100124},

	{"QM_CQE_AGGR_TIMEOUT_CTRL      ",  0x100144},

	{"ACC_RAS_MSI_INT_SEL           ",  0x1040fc},

	{"QM_CQE_OUT                    ",  0x104100},

	{"QM_EQE_OUT                    ",  0x104104},

	{"QM_AEQE_OUT                   ",  0x104108},

	{"QM_DB_INFO0                   ",  0x104180},

	{"QM_DB_INFO1                   ",  0x104184},

	{"QM_AM_CTRL_GLOBAL             ",  0x300000},

	{"QM_AM_CURR_PORT_STS           ",  0x300100},

	{"QM_AM_CURR_TRANS_RETURN       ",  0x300150},

	{"QM_AM_CURR_RD_MAX_TXID        ",  0x300154},

	{"QM_AM_CURR_WR_MAX_TXID        ",  0x300158},

	{"QM_AM_ALARM_RRESP             ",  0x300180},

	{"QM_AM_ALARM_BRESP             ",  0x300184},

};



static const struct debugfs_reg32 qm_vf_dfx_regs[] = {
@@ -1001,6 +1027,30 @@ static int qm_diff_regs_show(struct seq_file *s, void *unused) 
}

DEFINE_SHOW_ATTRIBUTE(qm_diff_regs);



static int qm_state_show(struct seq_file *s, void *unused)

{

	struct hisi_qm *qm = s->private;

	u32 val;

	int ret;



	ret = hisi_qm_get_dfx_access(qm);

	if (!ret) {

		val = readl(qm->io_base + QM_IN_IDLE_ST_REG);

		hisi_qm_put_dfx_access(qm);

	} else if (ret == -EAGAIN) {

		/* If device is in suspended, directly return the idle state. */

		val = QM_IN_IDLE_STATE;

	} else {

		return ret;

	}



	seq_printf(s, "%u\n", val);



	return 0;

}



DEFINE_SHOW_ATTRIBUTE(qm_state);



static ssize_t qm_status_read(struct file *filp, char __user *buffer,

			      size_t count, loff_t *pos)

{
@@ -1073,6 +1123,9 @@ void hisi_qm_debug_init(struct hisi_qm *qm) 


	/* only show this in PF */

	if (qm->fun_type == QM_HW_PF) {

		debugfs_create_file("qm_state", 0444, qm->debug.qm_d,

					qm, &qm_state_fops);



		qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);

		for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)

			qm_create_debugfs_file(qm, qm->debug.qm_d, i);

drivers/crypto/hisilicon/hpre/hpre_main.c

+27 −31
Original line number Diff line number Diff line
@@ -13,9 +13,7 @@ 
#include <linux/topology.h>

#include "hpre.h"



#define HPRE_QM_ABNML_INT_MASK		0x100004

#define HPRE_CTRL_CNT_CLR_CE_BIT	BIT(0)

#define HPRE_COMM_CNT_CLR_CE		0x0

#define HPRE_CTRL_CNT_CLR_CE		0x301000

#define HPRE_FSM_MAX_CNT		0x301008

#define HPRE_VFG_AXQOS			0x30100c
@@ -42,7 +40,6 @@ 
#define HPRE_HAC_INT_SET		0x301500

#define HPRE_RNG_TIMEOUT_NUM		0x301A34

#define HPRE_CORE_INT_ENABLE		0

#define HPRE_CORE_INT_DISABLE		GENMASK(21, 0)

#define HPRE_RDCHN_INI_ST		0x301a00

#define HPRE_CLSTR_BASE			0x302000

#define HPRE_CORE_EN_OFFSET		0x04
@@ -66,7 +63,6 @@ 
#define HPRE_CLSTR_ADDR_INTRVL		0x1000

#define HPRE_CLUSTER_INQURY		0x100

#define HPRE_CLSTR_ADDR_INQRY_RSLT	0x104

#define HPRE_TIMEOUT_ABNML_BIT		6

#define HPRE_PASID_EN_BIT		9

#define HPRE_REG_RD_INTVRL_US		10

#define HPRE_REG_RD_TMOUT_US		1000
@@ -203,9 +199,9 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { 
	{HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},

	{HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},

	{HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},

	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFFFE},

	{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE},

	{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE},

	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFC3E},

	{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFC3E},

	{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFC3E},

	{HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},

	{HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0,  0x4, 0x1},

	{HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},
@@ -358,6 +354,8 @@ static struct dfx_diff_registers hpre_diff_regs[] = { 
	},

};



static const struct hisi_qm_err_ini hpre_err_ini;



bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)

{

	u32 cap_val;
@@ -654,11 +652,6 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 
	writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);

	writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);



	/* HPRE need more time, we close this interrupt */

	val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK);

	val |= BIT(HPRE_TIMEOUT_ABNML_BIT);

	writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK);



	if (qm->ver >= QM_HW_V3)

		writel(HPRE_RSA_ENB | HPRE_ECC_ENB,

			qm->io_base + HPRE_TYPES_ENB);
@@ -667,9 +660,7 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 


	writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);

	writel(0x0, qm->io_base + HPRE_BD_ENDIAN);

	writel(0x0, qm->io_base + HPRE_INT_MASK);

	writel(0x0, qm->io_base + HPRE_POISON_BYPASS);

	writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE);

	writel(0x0, qm->io_base + HPRE_ECC_BYPASS);



	writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);
@@ -759,7 +750,7 @@ static void hpre_hw_error_disable(struct hisi_qm *qm) 


static void hpre_hw_error_enable(struct hisi_qm *qm)

{

	u32 ce, nfe;

	u32 ce, nfe, err_en;



	ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);

	nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
@@ -776,7 +767,8 @@ static void hpre_hw_error_enable(struct hisi_qm *qm) 
	hpre_master_ooo_ctrl(qm, true);



	/* enable hpre hw error interrupts */

	writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK);

	err_en = ce | nfe | HPRE_HAC_RAS_FE_ENABLE;

	writel(~err_en, qm->io_base + HPRE_INT_MASK);

}



static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file)
@@ -1162,6 +1154,7 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		qm->qp_num = pf_q_num;

		qm->debug.curr_qm_qp_num = pf_q_num;

		qm->qm_list = &hpre_devices;

		qm->err_ini = &hpre_err_ini;

		if (pf_q_num_flag)

			set_bit(QM_MODULE_PARAM, &qm->misc_ctl);

	}
@@ -1357,6 +1350,17 @@ static const struct hisi_qm_err_ini hpre_err_ini = { 
	.err_info_init		= hpre_err_info_init,

};



static void hpre_probe_uninit(struct hisi_qm *qm)

{

	if (qm->fun_type == QM_HW_VF)

		return;



	hpre_cnt_regs_clear(qm);

	qm->debug.curr_qm_qp_num = 0;

	hpre_show_last_regs_uninit(qm);

	hpre_close_sva_prefetch(qm);

}



static int hpre_pf_probe_init(struct hpre *hpre)

{

	struct hisi_qm *qm = &hpre->qm;
@@ -1367,10 +1371,6 @@ static int hpre_pf_probe_init(struct hpre *hpre) 
		return ret;



	hpre_open_sva_prefetch(qm);



	qm->err_ini = &hpre_err_ini;

	qm->err_ini->err_info_init(qm);

	hisi_qm_dev_err_init(qm);

	ret = hpre_show_last_regs_init(qm);

	if (ret)

		pci_err(qm->pdev, "Failed to init last word regs!\n");
@@ -1409,6 +1409,7 @@ static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
		return -ENOMEM;



	qm = &hpre->qm;

	set_bit(QM_DRIVER_DOWN, &qm->misc_ctl);

	ret = hpre_qm_init(qm, pdev);

	if (ret) {

		pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret);
@@ -1425,6 +1426,9 @@ static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	if (ret)

		goto err_with_err_init;



	/* Device is enabled, clear the flag. */

	clear_bit(QM_DRIVER_DOWN, &qm->misc_ctl);



	ret = hpre_debugfs_init(qm);

	if (ret)

		dev_warn(&pdev->dev, "init debugfs fail!\n");
@@ -1457,13 +1461,12 @@ static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 


err_qm_del_list:

	hisi_qm_del_list(qm, &hpre_devices);

	hisi_qm_wait_task_finish(qm, &hpre_devices);

	hpre_debugfs_exit(qm);

	hisi_qm_stop(qm, QM_NORMAL);



err_with_err_init:

	hpre_show_last_regs_uninit(qm);

	hisi_qm_dev_err_uninit(qm);



	hpre_probe_uninit(qm);

err_with_qm_init:

	hisi_qm_uninit(qm);
@@ -1483,14 +1486,7 @@ static void hpre_remove(struct pci_dev *pdev) 


	hpre_debugfs_exit(qm);

	hisi_qm_stop(qm, QM_NORMAL);



	if (qm->fun_type == QM_HW_PF) {

		hpre_cnt_regs_clear(qm);

		qm->debug.curr_qm_qp_num = 0;

		hpre_show_last_regs_uninit(qm);

		hisi_qm_dev_err_uninit(qm);

	}



	hpre_probe_uninit(qm);

	hisi_qm_uninit(qm);

}