Commit 59b8ca24 authored by Alex Hung's avatar Alex Hung Committed by Alex Deucher
Browse files

drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in dc 



[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.

This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in dc and dc/core directories.

Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5d3e1442

drivers/gpu/drm/amd/display/dc/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -63,9 +63,7 @@ DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink 
dc_surface.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \

dc_link_enc_cfg.o dc_link_dpia.o dc_link_dpcd.o



ifdef CONFIG_DRM_AMD_DC_DCN

DISPLAY_CORE += dc_vm_helper.o

endif



AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

+1 −2
Original line number Diff line number Diff line
@@ -65,7 +65,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2( 
	case DCE_VERSION_12_1:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

#if defined(CONFIG_DRM_AMD_DC_DCN)

	case DCN_VERSION_1_0:

	case DCN_VERSION_1_01:

	case DCN_VERSION_2_0:
@@ -80,7 +79,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( 
	case DCN_VERSION_3_16:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

#endif



	default:

		/* Unsupported DCE */

		BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/core/dc.c

+3 −28
Original line number Diff line number Diff line
@@ -829,14 +829,12 @@ static void dc_destruct(struct dc *dc) 
	kfree(dc->bw_dceip);

	dc->bw_dceip = NULL;



#ifdef CONFIG_DRM_AMD_DC_DCN

	kfree(dc->dcn_soc);

	dc->dcn_soc = NULL;



	kfree(dc->dcn_ip);

	dc->dcn_ip = NULL;



#endif

	kfree(dc->vm_helper);

	dc->vm_helper = NULL;
@@ -882,10 +880,8 @@ static bool dc_construct(struct dc *dc, 
	struct dc_context *dc_ctx;

	struct bw_calcs_dceip *dc_dceip;

	struct bw_calcs_vbios *dc_vbios;

#ifdef CONFIG_DRM_AMD_DC_DCN

	struct dcn_soc_bounding_box *dcn_soc;

	struct dcn_ip_params *dcn_ip;

#endif



	dc->config = init_params->flags;
@@ -913,7 +909,6 @@ static bool dc_construct(struct dc *dc, 
	}



	dc->bw_vbios = dc_vbios;

#ifdef CONFIG_DRM_AMD_DC_DCN

	dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);

	if (!dcn_soc) {

		dm_error("%s: failed to create dcn_soc\n", __func__);
@@ -929,7 +924,6 @@ static bool dc_construct(struct dc *dc, 
	}



	dc->dcn_ip = dcn_ip;

#endif



	if (!dc_construct_ctx(dc, init_params)) {

		dm_error("%s: failed to create ctx\n", __func__);
@@ -1868,7 +1862,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) 
	return (result == DC_OK);

}



#if defined(CONFIG_DRM_AMD_DC_DCN)

bool dc_acquire_release_mpc_3dlut(

		struct dc *dc, bool acquire,

		struct dc_stream_state *stream,
@@ -1904,7 +1897,7 @@ bool dc_acquire_release_mpc_3dlut( 
	}

	return ret;

}

#endif



static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)

{

	int i;
@@ -1925,7 +1918,6 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) 
	return false;

}



#ifdef CONFIG_DRM_AMD_DC_DCN

/* Perform updates here which need to be deferred until next vupdate

 *

 * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
@@ -1944,7 +1936,6 @@ static void process_deferred_updates(struct dc *dc) 
				dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);

	}

}

#endif /* CONFIG_DRM_AMD_DC_DCN */



void dc_post_update_surfaces_to_stream(struct dc *dc)

{
@@ -1971,9 +1962,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) 
			dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);

		}



#ifdef CONFIG_DRM_AMD_DC_DCN

	process_deferred_updates(dc);

#endif



	dc->hwss.optimize_bandwidth(dc, context);
@@ -1987,9 +1976,7 @@ static void init_state(struct dc *dc, struct dc_state *context) 
	 * initialize and obtain IP and SOC the base DML instance from DC is

	 * initially copied into every context

	 */

#ifdef CONFIG_DRM_AMD_DC_DCN

	memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));

#endif

}



struct dc_state *dc_create_state(struct dc *dc)
@@ -2361,11 +2348,9 @@ static enum surface_update_type check_update_surfaces_for_stream( 
	int i;

	enum surface_update_type overall_type = UPDATE_TYPE_FAST;



#if defined(CONFIG_DRM_AMD_DC_DCN)

	if (dc->idle_optimizations_allowed)

		overall_type = UPDATE_TYPE_FULL;



#endif

	if (stream_status == NULL || stream_status->plane_count != surface_count)

		overall_type = UPDATE_TYPE_FULL;
@@ -2874,10 +2859,8 @@ static void commit_planes_for_stream(struct dc *dc, 
	}



	if (update_type == UPDATE_TYPE_FULL) {

#if defined(CONFIG_DRM_AMD_DC_DCN)

		dc_allow_idle_optimizations(dc, false);



#endif

		if (get_seamless_boot_stream_count(context) == 0)

			dc->hwss.prepare_bandwidth(dc, context);
@@ -2895,7 +2878,6 @@ static void commit_planes_for_stream(struct dc *dc, 
		}

	}



#ifdef CONFIG_DRM_AMD_DC_DCN

	if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {

		struct pipe_ctx *mpcc_pipe;

		struct pipe_ctx *odm_pipe;
@@ -2904,7 +2886,6 @@ static void commit_planes_for_stream(struct dc *dc, 
			for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

				odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;

	}

#endif



	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)

		if (top_pipe_to_program &&
@@ -3014,7 +2995,6 @@ static void commit_planes_for_stream(struct dc *dc, 
	}

	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {

		dc->hwss.program_front_end_for_ctx(dc, context);

#ifdef CONFIG_DRM_AMD_DC_DCN

		if (dc->debug.validate_dml_output) {

			for (i = 0; i < dc->res_pool->pipe_count; i++) {

				struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
@@ -3028,7 +3008,6 @@ static void commit_planes_for_stream(struct dc *dc, 
						&context->res_ctx.pipe_ctx[i].ttu_regs);

			}

		}

#endif

	}



	// Update Type FAST, Surface updates
@@ -3583,8 +3562,6 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable) 
	return true;

}



#if defined(CONFIG_DRM_AMD_DC_DCN)



void dc_allow_idle_optimizations(struct dc *dc, bool allow)

{

	if (dc->debug.disable_idle_power_optimizations)
@@ -3740,7 +3717,6 @@ void dc_hardware_release(struct dc *dc) 
	if (dc->hwss.hardware_release)

		dc->hwss.hardware_release(dc);

}

#endif



/*

 *****************************************************************************
@@ -3760,13 +3736,12 @@ void dc_hardware_release(struct dc *dc) 
 */

bool dc_is_dmub_outbox_supported(struct dc *dc)

{

#if defined(CONFIG_DRM_AMD_DC_DCN)

	/* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */

	/* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */

	if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&

	    dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&

	    !dc->debug.dpia_debug.bits.disable_dpia)

		return true;

#endif



	/* dmub aux needs dmub notifications to be enabled */

	return dc->debug.enable_dmub_aux_for_legacy_ddc;

}

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

+0 −2
Original line number Diff line number Diff line
@@ -345,7 +345,6 @@ void context_clock_trace( 
		struct dc *dc,

		struct dc_state *context)

{

#if defined(CONFIG_DRM_AMD_DC_DCN)

	DC_LOGGER_INIT(dc->ctx->logger);

	CLOCK_TRACE("Current: dispclk_khz:%d  max_dppclk_khz:%d  dcfclk_khz:%d\n"

			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n",
@@ -363,7 +362,6 @@ void context_clock_trace( 
			context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

			context->bw_ctx.bw.dcn.clk.fclk_khz,

			context->bw_ctx.bw.dcn.clk.socclk_khz);

#endif

}



/**

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+0 −2
Original line number Diff line number Diff line
@@ -804,7 +804,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link) 


static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)

{

#if defined(CONFIG_DRM_AMD_DC_DCN)

	/* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock

	 * reports DSC support.

	 */
@@ -815,7 +814,6 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) 
			link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&

			!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)

		link->wa_flags.dpia_mst_dsc_always_on = true;

#endif

}



static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)