Commit 59954972 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull powerpc fixes from Michael Ellerman:

 - Fix handling of PCI domains in /proc on 32-bit systems using the
   recently added support for numbering buses from zero for each domain.

 - A fix and a revert for some changes to use READ/WRITE_ONCE() which
   caused problems with KASAN enabled due to sanitisation calls being
   introduced in low-level paths that can't cope with it.

 - Fix build errors on 32-bit caused by the syscall table being
   misaligned sometimes.

 - Two fixes to get IBM Cell native machines booting again, which had
   bit-rotted while my QS22 was temporarily out of action.

 - Fix the papr_scm driver to not assume the order of events returned by
   the hypervisor is stable, and a related compile fix.

Thanks to Aneesh Kumar K.V, Christophe Leroy, Jordan Niethe, Kajol Jain,
Masahiro Yamada, Nathan Chancellor, Pali Rohár, Vaibhav Jain, and Zhouyi
Zhou.

* tag 'powerpc-6.0-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/papr_scm: Ensure rc is always initialized in papr_scm_pmu_register()
  Revert "powerpc/irq: Don't open code irq_soft_mask helpers"
  powerpc: Fix hard_irq_disable() with sanitizer
  powerpc/rtas: Fix RTAS MSR[HV] handling for Cell
  Revert "powerpc: Remove unused FW_FEATURE_NATIVE references"
  powerpc: align syscall table for ppc32
  powerpc/pci: Enable PCI domains in /proc when PCI bus numbers are not unique
  powerpc/papr_scm: Fix nvdimm event mappings
parents 685ed983 6cf07810
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+8 −0
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ enum {
	FW_FEATURE_POWERNV_ALWAYS = 0,
	FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
	FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
	FW_FEATURE_NATIVE_POSSIBLE = 0,
	FW_FEATURE_NATIVE_ALWAYS = 0,
	FW_FEATURE_POSSIBLE =
#ifdef CONFIG_PPC_PSERIES
		FW_FEATURE_PSERIES_POSSIBLE |
@@ -92,6 +94,9 @@ enum {
#endif
#ifdef CONFIG_PPC_PS3
		FW_FEATURE_PS3_POSSIBLE |
#endif
#ifdef CONFIG_PPC_HASH_MMU_NATIVE
		FW_FEATURE_NATIVE_ALWAYS |
#endif
		0,
	FW_FEATURE_ALWAYS =
@@ -103,6 +108,9 @@ enum {
#endif
#ifdef CONFIG_PPC_PS3
		FW_FEATURE_PS3_ALWAYS &
#endif
#ifdef CONFIG_PPC_HASH_MMU_NATIVE
		FW_FEATURE_NATIVE_ALWAYS &
#endif
		FW_FEATURE_POSSIBLE,

+38 −8
Original line number Diff line number Diff line
@@ -113,7 +113,14 @@ static inline void __hard_RI_enable(void)

static inline notrace unsigned long irq_soft_mask_return(void)
{
	return READ_ONCE(local_paca->irq_soft_mask);
	unsigned long flags;

	asm volatile(
		"lbz %0,%1(13)"
		: "=r" (flags)
		: "i" (offsetof(struct paca_struct, irq_soft_mask)));

	return flags;
}

/*
@@ -140,24 +147,46 @@ static inline notrace void irq_soft_mask_set(unsigned long mask)
	if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
		WARN_ON(mask && !(mask & IRQS_DISABLED));

	WRITE_ONCE(local_paca->irq_soft_mask, mask);
	barrier();
	asm volatile(
		"stb %0,%1(13)"
		:
		: "r" (mask),
		  "i" (offsetof(struct paca_struct, irq_soft_mask))
		: "memory");
}

static inline notrace unsigned long irq_soft_mask_set_return(unsigned long mask)
{
	unsigned long flags = irq_soft_mask_return();
	unsigned long flags;

#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
	WARN_ON(mask && !(mask & IRQS_DISABLED));
#endif

	irq_soft_mask_set(mask);
	asm volatile(
		"lbz %0,%1(13); stb %2,%1(13)"
		: "=&r" (flags)
		: "i" (offsetof(struct paca_struct, irq_soft_mask)),
		  "r" (mask)
		: "memory");

	return flags;
}

static inline notrace unsigned long irq_soft_mask_or_return(unsigned long mask)
{
	unsigned long flags = irq_soft_mask_return();
	unsigned long flags, tmp;

	irq_soft_mask_set(flags | mask);
	asm volatile(
		"lbz %0,%2(13); or %1,%0,%3; stb %1,%2(13)"
		: "=&r" (flags), "=r" (tmp)
		: "i" (offsetof(struct paca_struct, irq_soft_mask)),
		  "r" (mask)
		: "memory");

#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
	WARN_ON((mask | flags) && !((mask | flags) & IRQS_DISABLED));
#endif

	return flags;
}
@@ -282,7 +311,8 @@ static inline bool pmi_irq_pending(void)
	flags = irq_soft_mask_set_return(IRQS_ALL_DISABLED);		\
	local_paca->irq_happened |= PACA_IRQ_HARD_DIS;			\
	if (!arch_irqs_disabled_flags(flags)) {				\
		WRITE_ONCE(local_paca->saved_r1, current_stack_pointer);\
		asm volatile("std%X0 %1,%0" : "=m" (local_paca->saved_r1) \
					    : "r" (current_stack_pointer)); \
		trace_hardirqs_off();					\
	}								\
} while(0)
+9 −0
Original line number Diff line number Diff line
@@ -245,6 +245,15 @@ static int __init pcibios_init(void)

	printk(KERN_INFO "PCI: Probing PCI hardware\n");

#ifdef CONFIG_PPC_PCI_BUS_NUM_DOMAIN_DEPENDENT
	/*
	 * Enable PCI domains in /proc when PCI bus numbers are not unique
	 * across all PCI domains to prevent conflicts. And keep PCI domain 0
	 * backward compatible in /proc for video cards.
	 */
	pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
#endif

	if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
		pci_assign_all_buses = 1;

+4 −0
Original line number Diff line number Diff line
@@ -109,8 +109,12 @@ __enter_rtas:
	 * its critical regions (as specified in PAPR+ section 7.2.1). MSR[S]
	 * is not impacted by RFI_TO_KERNEL (only urfid can unset it). So if
	 * MSR[S] is set, it will remain when entering RTAS.
	 * If we're in HV mode, RTAS must also run in HV mode, so extract MSR_HV
	 * from the saved MSR value and insert into the value RTAS will use.
	 */
	extrdi	r0, r6, 1, 63 - MSR_HV_LG
	LOAD_REG_IMMEDIATE(r6, MSR_ME | MSR_RI)
	insrdi	r6, r0, 1, 63 - MSR_HV_LG

	li      r0,0
	mtmsrd  r0,1                    /* disable RI before using SRR0/1 */
+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@
	.p2align	3
#define __SYSCALL(nr, entry)	.8byte entry
#else
	.p2align	2
#define __SYSCALL(nr, entry)	.long entry
#endif

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