Commit 59802074 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Refresh westmereep-dp events 

Update the westmereep-dp events using the new tooling from:

  https://github.com/intel/perfmon



The events are unchanged, unused json values are removed and the
version number bumped to v3 to match the perfmon mapfile.csv. This
increases consistency across the json files.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-22-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 69f685e0

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core 
GenuineIntel-6-55-[01234],v1.28,skylakex,core

GenuineIntel-6-86,v1.20,snowridgex,core

GenuineIntel-6-8[CD],v1.08,tigerlake,core

GenuineIntel-6-2C,v2,westmereep-dp,core

GenuineIntel-6-2C,v3,westmereep-dp,core

GenuineIntel-6-25,v3,westmereep-sp,core

GenuineIntel-6-2F,v3,westmereex,core

AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core

tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json

+0 −445

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json

+0 −28
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "X87 Floating point assists (Precise Event)",

        "Counter": "0,1,2,3",

        "EventCode": "0xF7",

        "EventName": "FP_ASSIST.ALL",

        "PEBS": "1",
@@ -10,7 +9,6 @@ 
    },

    {

        "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",

        "Counter": "0,1,2,3",

        "EventCode": "0xF7",

        "EventName": "FP_ASSIST.INPUT",

        "PEBS": "1",
@@ -19,7 +17,6 @@ 
    },

    {

        "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",

        "Counter": "0,1,2,3",

        "EventCode": "0xF7",

        "EventName": "FP_ASSIST.OUTPUT",

        "PEBS": "1",
@@ -28,7 +25,6 @@ 
    },

    {

        "BriefDescription": "MMX Uops",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.MMX",

        "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@ 
    },

    {

        "BriefDescription": "SSE2 integer Uops",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",

        "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@ 
    },

    {

        "BriefDescription": "SSE* FP double precision Uops",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",

        "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@ 
    },

    {

        "BriefDescription": "SSE and SSE2 FP Uops",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_FP",

        "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@ 
    },

    {

        "BriefDescription": "SSE FP packed Uops",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",

        "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@ 
    },

    {

        "BriefDescription": "SSE FP scalar Uops",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",

        "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@ 
    },

    {

        "BriefDescription": "SSE* FP single precision Uops",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",

        "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@ 
    },

    {

        "BriefDescription": "Computational floating-point operations executed",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.X87",

        "SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@ 
    },

    {

        "BriefDescription": "All Floating Point to and from MMX transitions",

        "Counter": "0,1,2,3",

        "EventCode": "0xCC",

        "EventName": "FP_MMX_TRANS.ANY",

        "SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@ 
    },

    {

        "BriefDescription": "Transitions from MMX to Floating Point instructions",

        "Counter": "0,1,2,3",

        "EventCode": "0xCC",

        "EventName": "FP_MMX_TRANS.TO_FP",

        "SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@ 
    },

    {

        "BriefDescription": "Transitions from Floating Point to MMX instructions",

        "Counter": "0,1,2,3",

        "EventCode": "0xCC",

        "EventName": "FP_MMX_TRANS.TO_MMX",

        "SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@ 
    },

    {

        "BriefDescription": "128 bit SIMD integer pack operations",

        "Counter": "0,1,2,3",

        "EventCode": "0x12",

        "EventName": "SIMD_INT_128.PACK",

        "SampleAfterValue": "200000",
@@ -124,7 +109,6 @@ 
    },

    {

        "BriefDescription": "128 bit SIMD integer arithmetic operations",

        "Counter": "0,1,2,3",

        "EventCode": "0x12",

        "EventName": "SIMD_INT_128.PACKED_ARITH",

        "SampleAfterValue": "200000",
@@ -132,7 +116,6 @@ 
    },

    {

        "BriefDescription": "128 bit SIMD integer logical operations",

        "Counter": "0,1,2,3",

        "EventCode": "0x12",

        "EventName": "SIMD_INT_128.PACKED_LOGICAL",

        "SampleAfterValue": "200000",
@@ -140,7 +123,6 @@ 
    },

    {

        "BriefDescription": "128 bit SIMD integer multiply operations",

        "Counter": "0,1,2,3",

        "EventCode": "0x12",

        "EventName": "SIMD_INT_128.PACKED_MPY",

        "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@ 
    },

    {

        "BriefDescription": "128 bit SIMD integer shift operations",

        "Counter": "0,1,2,3",

        "EventCode": "0x12",

        "EventName": "SIMD_INT_128.PACKED_SHIFT",

        "SampleAfterValue": "200000",
@@ -156,7 +137,6 @@ 
    },

    {

        "BriefDescription": "128 bit SIMD integer shuffle/move operations",

        "Counter": "0,1,2,3",

        "EventCode": "0x12",

        "EventName": "SIMD_INT_128.SHUFFLE_MOVE",

        "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@ 
    },

    {

        "BriefDescription": "128 bit SIMD integer unpack operations",

        "Counter": "0,1,2,3",

        "EventCode": "0x12",

        "EventName": "SIMD_INT_128.UNPACK",

        "SampleAfterValue": "200000",
@@ -172,7 +151,6 @@ 
    },

    {

        "BriefDescription": "SIMD integer 64 bit pack operations",

        "Counter": "0,1,2,3",

        "EventCode": "0xFD",

        "EventName": "SIMD_INT_64.PACK",

        "SampleAfterValue": "200000",
@@ -180,7 +158,6 @@ 
    },

    {

        "BriefDescription": "SIMD integer 64 bit arithmetic operations",

        "Counter": "0,1,2,3",

        "EventCode": "0xFD",

        "EventName": "SIMD_INT_64.PACKED_ARITH",

        "SampleAfterValue": "200000",
@@ -188,7 +165,6 @@ 
    },

    {

        "BriefDescription": "SIMD integer 64 bit logical operations",

        "Counter": "0,1,2,3",

        "EventCode": "0xFD",

        "EventName": "SIMD_INT_64.PACKED_LOGICAL",

        "SampleAfterValue": "200000",
@@ -196,7 +172,6 @@ 
    },

    {

        "BriefDescription": "SIMD integer 64 bit packed multiply operations",

        "Counter": "0,1,2,3",

        "EventCode": "0xFD",

        "EventName": "SIMD_INT_64.PACKED_MPY",

        "SampleAfterValue": "200000",
@@ -204,7 +179,6 @@ 
    },

    {

        "BriefDescription": "SIMD integer 64 bit shift operations",

        "Counter": "0,1,2,3",

        "EventCode": "0xFD",

        "EventName": "SIMD_INT_64.PACKED_SHIFT",

        "SampleAfterValue": "200000",
@@ -212,7 +186,6 @@ 
    },

    {

        "BriefDescription": "SIMD integer 64 bit shuffle/move operations",

        "Counter": "0,1,2,3",

        "EventCode": "0xFD",

        "EventName": "SIMD_INT_64.SHUFFLE_MOVE",

        "SampleAfterValue": "200000",
@@ -220,7 +193,6 @@ 
    },

    {

        "BriefDescription": "SIMD integer 64 bit unpack operations",

        "Counter": "0,1,2,3",

        "EventCode": "0xFD",

        "EventName": "SIMD_INT_64.UNPACK",

        "SampleAfterValue": "200000",

tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json

+0 −3
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Instructions decoded",

        "Counter": "0,1,2,3",

        "EventCode": "0xD0",

        "EventName": "MACRO_INSTS.DECODED",

        "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@ 
    },

    {

        "BriefDescription": "Macro-fused instructions decoded",

        "Counter": "0,1,2,3",

        "EventCode": "0xA6",

        "EventName": "MACRO_INSTS.FUSIONS_DECODED",

        "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@ 
    },

    {

        "BriefDescription": "Two Uop instructions decoded",

        "Counter": "0,1,2,3",

        "EventCode": "0x19",

        "EventName": "TWO_UOP_INSTS_DECODED",

        "SampleAfterValue": "2000000",

tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json

+0 −137

File changed.

Preview size limit exceeded, changes collapsed.