Commit 5969e0c1 authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
Browse files

powerpc/perf: Update MMCR2 to support event exclude_idle 



struct perf_event_attr supports exclude counting of idle task.
This is sent to kernel via perf_event_attr.exclude_idle and
in perf tool, user can use ":I" event modifier to enable this
for specific event.

Monitor Mode Control Register 2 (MMCR2) SPR has control bits
for each PMCs to freeze counting based on the Control Register
CTRL[RUN] state. CTRL[RUN] is not set when idle task is
running. Patch adds a check for event attr.exclude_idle to
set MMCR2[FCnWAIT] bit.

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210429050208.266619-1-maddy@linux.ibm.com
parent a28a2eff

arch/powerpc/perf/isa207-common.c

+3 −0
Original line number Diff line number Diff line
@@ -686,6 +686,9 @@ int isa207_compute_mmcr(u64 event[], int n_ev, 
				mmcr2 |= MMCR2_FCS(pmc);

		}



		if (pevents[i]->attr.exclude_idle)

			mmcr2 |= MMCR2_FCWAIT(pmc);



		if (cpu_has_feature(CPU_FTR_ARCH_31)) {

			if (pmc <= 4) {

				val = (event[i] >> p10_EVENT_MMCR3_SHIFT) &

arch/powerpc/perf/isa207-common.h

+1 −0
Original line number Diff line number Diff line
@@ -249,6 +249,7 @@ 
/* Bits in MMCR2 for PowerISA v2.07 */

#define MMCR2_FCS(pmc)			(1ull << (63 - (((pmc) - 1) * 9)))

#define MMCR2_FCP(pmc)			(1ull << (62 - (((pmc) - 1) * 9)))

#define MMCR2_FCWAIT(pmc)		(1ull << (58 - (((pmc) - 1) * 9)))

#define MMCR2_FCH(pmc)			(1ull << (57 - (((pmc) - 1) * 9)))



#define MAX_ALT				2