Commit 594b237b authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Add interface to track PHY state 



[Why]
Sometimes pixel clock needs to remain active after transmitter disable.

[How]
Use update_phy_state to track PHY state after stream
enable/disable and program pixel clock as needed.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarTaimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b68ea8af

drivers/gpu/drm/amd/display/dc/core/dc.c

+15 −3
Original line number Diff line number Diff line
@@ -1180,6 +1180,10 @@ static void disable_vbios_mode_if_required( 
						pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;



					if (pix_clk_100hz != requested_pix_clk_100hz) {

						if (dc->hwss.update_phy_state)

							dc->hwss.update_phy_state(dc->current_state,

									pipe, TX_OFF_SYMCLK_OFF);

						else

							core_link_disable_stream(pipe);

						pipe->stream->dpms_off = false;

					}
@@ -3063,6 +3067,10 @@ static void commit_planes_do_stream_update(struct dc *dc, 


			if (stream_update->dpms_off) {

				if (*stream_update->dpms_off) {

					if (dc->hwss.update_phy_state)

						dc->hwss.update_phy_state(dc->current_state,

								pipe_ctx, TX_OFF_SYMCLK_ON);

					else

						core_link_disable_stream(pipe_ctx);

					/* for dpms, keep acquired resources*/

					if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
@@ -3074,6 +3082,10 @@ static void commit_planes_do_stream_update(struct dc *dc, 
					if (get_seamless_boot_stream_count(context) == 0)

						dc->hwss.prepare_bandwidth(dc, dc->current_state);



					if (dc->hwss.update_phy_state)

						dc->hwss.update_phy_state(dc->current_state,

								pipe_ctx, TX_ON_SYMCLK_ON);

					else

						core_link_enable_stream(dc->current_state, pipe_ctx);

				}

			}

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+10 −2
Original line number Diff line number Diff line
@@ -4519,6 +4519,10 @@ void dc_link_dp_handle_link_loss(struct dc_link *link) 
		pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

		if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&

				pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {

			if (link->dc->hwss.update_phy_state)

				link->dc->hwss.update_phy_state(link->dc->current_state,

						pipe_ctx, TX_OFF_SYMCLK_OFF);

			else

				core_link_disable_stream(pipe_ctx);

		}

	}
@@ -4527,6 +4531,10 @@ void dc_link_dp_handle_link_loss(struct dc_link *link) 
		pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

		if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&

				pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {

			if (link->dc->hwss.update_phy_state)

				link->dc->hwss.update_phy_state(link->dc->current_state,

						pipe_ctx, TX_ON_SYMCLK_ON);

			else

				core_link_enable_stream(link->dc->current_state, pipe_ctx);

		}

	}

drivers/gpu/drm/amd/display/dc/dc_link.h

+1 −0
Original line number Diff line number Diff line
@@ -232,6 +232,7 @@ struct dc_link { 


	struct gpio *hpd_gpio;

	enum dc_link_fec_state fec_state;

	enum phy_state phy_state;

};



const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+6 −2
Original line number Diff line number Diff line
@@ -1577,8 +1577,12 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
	if (dc_is_dp_signal(pipe_ctx->stream->signal))

		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);



	if (!stream->dpms_off)

	if (!stream->dpms_off) {

		if (dc->hwss.update_phy_state)

			dc->hwss.update_phy_state(context, pipe_ctx, TX_ON_SYMCLK_ON);

		else

			core_link_enable_stream(context, pipe_ctx);

	}



	/* DCN3.1 FPGA Workaround

	 * Need to enable HPO DP Stream Encoder before setting OTG master enable.

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+6 −3
Original line number Diff line number Diff line
@@ -2361,9 +2361,12 @@ static void dcn20_reset_back_end_for_pipe( 
		 * screen only, the dpms_off would be true but

		 * VBIOS lit up eDP, so check link status too.

		 */

		if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

		if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) {

			if (dc->hwss.update_phy_state)

				dc->hwss.update_phy_state(dc->current_state, pipe_ctx, TX_OFF_SYMCLK_OFF);

			else

				core_link_disable_stream(pipe_ctx);

		else if (pipe_ctx->stream_res.audio)

		} else if (pipe_ctx->stream_res.audio)

			dc->hwss.disable_audio_stream(pipe_ctx);



		/* free acquired resources */