Unverified Commit 59486969 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v6.6-rockchip-dts32-1' of... 

Merge tag 'v6.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

Basic graphics support for rv1126, some more new peripherals for it as well
and some improvements for the edgeble-neu2 board based on this soc.

* tag 'v6.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Add rv1126 VOP_LITE support
  ARM: dts: rockchip: Add rv1126 PD_VO entry
  ARM: dts: rockchip: Add 12V main supply for edgeble-neu2
  ARM: dts: rockchip: Add 3V3_SYS regulator for edgeble-neu2
  ARM: dts: rockchip: Enable SFC for edgeble-neu2
  ARM: dts: rockchip: Drop EMMC_RSTN for edgeble-neu2
  ARM: dts: rockchip: Add rv1126 uart5m2_xfer pins
  ARM: dts: rockchip: Add rv1126 FSPI pins
  ARM: dts: rockchip: Add SFC node to rv1126

Link: https://lore.kernel.org/r/6299163.hdfAi7Kttb@phil


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents b89c940f 1bf0dcb1

arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts

+29 −0
Original line number Diff line number Diff line
@@ -20,6 +20,35 @@ 
	chosen {

		stdout-path = "serial2:1500000n8";

	};



	vcc12v_dcin: vcc12v-dcin-regulator {

		compatible = "regulator-fixed";

		regulator-name = "vcc12v_dcin";

		regulator-always-on;

		regulator-boot-on;

		regulator-min-microvolt = <12000000>;

		regulator-max-microvolt = <12000000>;

	};



	vcc5v0_sys: vcc5v0-sys-regulator {

		compatible = "regulator-fixed";

		regulator-name = "vcc5v0_sys";

		regulator-always-on;

		regulator-boot-on;

		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;

		vin-supply = <&vcc12v_dcin>;

	};



	v3v3_sys: v3v3-sys-regulator {

		compatible = "regulator-fixed";

		regulator-name = "v3v3_sys";

		regulator-always-on;

		regulator-boot-on;

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc5v0_sys>;

	};

};



&gmac {

arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi

+17 −10
Original line number Diff line number Diff line
@@ -11,15 +11,6 @@ 
		mmc0 = &emmc;

	};



	vcc5v0_sys: vcc5v0-sys-regulator {

		compatible = "regulator-fixed";

		regulator-name = "vcc5v0_sys";

		regulator-always-on;

		regulator-boot-on;

		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;

	};



	vccio_flash: vccio-flash-regulator {

		compatible = "regulator-fixed";

		enable-active-high;
@@ -52,7 +43,7 @@ 
	bus-width = <8>;

	non-removable;

	pinctrl-names = "default";

	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;

	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;

	rockchip,default-sample-phase = <90>;

	vmmc-supply = <&vcc_3v3>;

	vqmmc-supply = <&vccio_flash>;
@@ -301,6 +292,22 @@ 
	status = "okay";

};



&sfc {

	pinctrl-names = "default";

	pinctrl-0 = <&fspi_pins>;

	#address-cells = <1>;

	#size-cells = <0>;

	status = "okay";



	flash@0 {

		compatible = "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <50000000>;

		spi-rx-bus-width = <4>;

		spi-tx-bus-width = <1>;

	};

};



&sdio {

	bus-width = <4>;

	cap-sd-highspeed;

arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -59,6 +59,24 @@ 
				<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;

		};

	};

	fspi {

		/omit-if-no-ref/

		fspi_pins: fspi-pins {

			rockchip,pins =

				/* fspi_clk */

				<1 RK_PA3 3 &pcfg_pull_down>,

				/* fspi_cs0n */

				<0 RK_PD4 3 &pcfg_pull_up>,

				/* fspi_d0 */

				<1 RK_PA0 3 &pcfg_pull_up>,

				/* fspi_d1 */

				<1 RK_PA1 3 &pcfg_pull_up>,

				/* fspi_d2 */

				<0 RK_PD6 3 &pcfg_pull_up>,

				/* fspi_d3 */

				<1 RK_PA2 3 &pcfg_pull_up>;

		};

	};

	i2c0 {

		/omit-if-no-ref/

		i2c0_xfer: i2c0-xfer {
@@ -249,5 +267,13 @@ 
				/* uart5_tx_m0 */

				<3 RK_PA6 4 &pcfg_pull_up>;

		};

		/omit-if-no-ref/

		uart5m2_xfer: uart5m2-xfer {

			rockchip,pins =

				/* uart5_rx_m2 */

				<2 RK_PA1 3 &pcfg_pull_up>,

				/* uart5_tx_m2 */

				<2 RK_PA0 3 &pcfg_pull_up>;

		};

	};

};

arch/arm/boot/dts/rockchip/rv1126.dtsi

+93 −0
Original line number Diff line number Diff line
@@ -83,6 +83,11 @@ 
		clock-frequency = <24000000>;

	};



	display_subsystem {

		compatible = "rockchip,display-subsystem";

		ports = <&vop_out>;

	};



	xin24m: oscillator {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;
@@ -125,6 +130,26 @@ 
		reg = <0xfe86c000 0x20>;

	};



	qos_iep: qos@fe8a0000 {

		compatible = "rockchip,rv1126-qos", "syscon";

		reg = <0xfe8a0000 0x20>;

	};



	qos_rga_rd: qos@fe8a0080 {

		compatible = "rockchip,rv1126-qos", "syscon";

		reg = <0xfe8a0080 0x20>;

	};



	qos_rga_wr: qos@fe8a0100 {

		compatible = "rockchip,rv1126-qos", "syscon";

		reg = <0xfe8a0100 0x20>;

	};



	qos_vop: qos@fe8a0180 {

		compatible = "rockchip,rv1126-qos", "syscon";

		reg = <0xfe8a0180 0x20>;

	};



	gic: interrupt-controller@feff0000 {

		compatible = "arm,gic-400";

		interrupt-controller;
@@ -170,6 +195,25 @@ 
				pm_qos = <&qos_sdio>;

				#power-domain-cells = <0>;

			};



			power-domain@RV1126_PD_VO {

				reg = <RV1126_PD_VO>;

				clocks = <&cru ACLK_RGA>,

					 <&cru HCLK_RGA>,

					 <&cru CLK_RGA_CORE>,

					 <&cru ACLK_VOP>,

					 <&cru HCLK_VOP>,

					 <&cru DCLK_VOP>,

					 <&cru PCLK_DSIHOST>,

					 <&cru ACLK_IEP>,

					 <&cru HCLK_IEP>,

					 <&cru CLK_IEP_CORE>;

				pm_qos = <&qos_rga_rd>,

					 <&qos_rga_wr>,

					 <&qos_vop>,

					 <&qos_iep>;

				#power-domain-cells = <0>;

			};

		};

	};
@@ -332,6 +376,43 @@ 
		clock-names = "pclk", "timer";

	};



	vop: vop@ffb00000 {

		compatible = "rockchip,rv1126-vop";

		reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;

		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;

		reset-names = "axi", "ahb", "dclk";

		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;

		iommus = <&vop_mmu>;

		power-domains = <&power RV1126_PD_VO>;

		status = "disabled";



		vop_out: port {

			#address-cells = <1>;

			#size-cells = <0>;



			vop_out_rgb: endpoint@0 {

				reg = <0>;

			};



			vop_out_dsi: endpoint@1 {

				reg = <1>;

			};

		};

	};



	vop_mmu: iommu@ffb00f00 {

		compatible = "rockchip,iommu";

		reg = <0xffb00f00 0x100>;

		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "aclk", "iface";

		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;

		#iommu-cells = <0>;

		power-domains = <&power RV1126_PD_VO>;

		status = "disabled";

	};



	gmac: ethernet@ffc40000 {

		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";

		reg = <0xffc40000 0x4000>;
@@ -419,6 +500,18 @@ 
		status = "disabled";

	};



	sfc: spi@ffc90000  {

		compatible = "rockchip,sfc";

		reg = <0xffc90000 0x4000>;

		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;

		assigned-clocks = <&cru SCLK_SFC>;

		assigned-clock-rates = <80000000>;

		clock-names = "clk_sfc", "hclk_sfc";

		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;

		power-domains = <&power RV1126_PD_NVM>;

		status = "disabled";

	};



	pinctrl: pinctrl {

		compatible = "rockchip,rv1126-pinctrl";

		rockchip,grf = <&grf>;