Commit 593dea00 authored by Miquel Raynal's avatar Miquel Raynal Committed by Greg Kroah-Hartman
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serial: 8250: dw: Allow to use a fallback CPR value if not synthesized 



DW UART controllers can be synthesized without the CPR register.
In this case, allow to the platform information to provide a CPR value.

Co-developed-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20220422180615.9098-5-miquel.raynal@bootlin.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ffd38144

drivers/tty/serial/8250/8250_dwlib.c

+7 −3
Original line number Diff line number Diff line
@@ -89,6 +89,8 @@ EXPORT_SYMBOL_GPL(dw8250_do_set_termios); 


void dw8250_setup_port(struct uart_port *p)

{

	struct dw8250_port_data *pd = p->private_data;

	struct dw8250_data *data = to_dw8250_data(pd);

	struct uart_8250_port *up = up_to_u8250p(p);

	u32 reg;
@@ -108,14 +110,16 @@ void dw8250_setup_port(struct uart_port *p) 
	dw8250_writel_ext(p, DW_UART_DLF, 0);



	if (reg) {

		struct dw8250_port_data *d = p->private_data;



		d->dlf_size = fls(reg);

		pd->dlf_size = fls(reg);

		p->get_divisor = dw8250_get_divisor;

		p->set_divisor = dw8250_set_divisor;

	}



	reg = dw8250_readl_ext(p, DW_UART_CPR);

	if (!reg) {

		reg = data->pdata->cpr_val;

		dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);

	}

	if (!reg)

		return;

drivers/tty/serial/8250/8250_dwlib.h

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ struct dw8250_port_data { 


struct dw8250_platform_data {

	u8 usr_reg;

	u32 cpr_val;

	unsigned int quirks;

};