Commit 591de9fb authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8: add mu5/6 node 



Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
communicating with general purpose Cortex-M4 cores.

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 75e4493e

arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -141,6 +141,22 @@ lsio_subsys: bus@5d000000 { 
		status = "disabled";

	};



	lsio_mu5: mailbox@5d200000 {

		reg = <0x5d200000 0x10000>;

		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;

		#mbox-cells = <2>;

		power-domains = <&pd IMX_SC_R_MU_5A>;

		status = "disabled";

	};



	lsio_mu6: mailbox@5d210000 {

		reg = <0x5d210000 0x10000>;

		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;

		#mbox-cells = <2>;

		power-domains = <&pd IMX_SC_R_MU_6A>;

		status = "disabled";

	};



	lsio_mu13: mailbox@5d280000 {

		reg = <0x5d280000 0x10000>;

		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -56,6 +56,14 @@ 
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";

};



&lsio_mu5 {

	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";

};



&lsio_mu6 {

	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";

};



&lsio_mu13 {

	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";

};

arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -56,6 +56,14 @@ 
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

};



&lsio_mu5 {

	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

};



&lsio_mu6 {

	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

};



&lsio_mu13 {

	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

};