Commit 591b00cc authored by Raphael Gallais-Pou's avatar Raphael Gallais-Pou Committed by Rob Herring
Browse files

dt-bindings: irqchip: convert st,stih407-irq-syscfg to DT schema 



Convert deprecated format to DT schema format.

Signed-off-by: default avatarRaphael Gallais-Pou <rgallaispou@gmail.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230905072740.23859-1-rgallaispou@gmail.com


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 274e4809

Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt

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STMicroelectronics STi System Configuration Controlled IRQs

-----------------------------------------------------------



On STi based systems; External, CTI (Core Sight), PMU (Performance Management),

and PL310 L2 Cache IRQs are controlled using System Configuration registers.

This driver is used to unmask them prior to use.



Required properties:

- compatible	: Should be "st,stih407-irq-syscfg"

- st,syscfg	: Phandle to Cortex-A9 IRQ system config registers

- st,irq-device	: Array of IRQs to enable - should be 2 in length

- st,fiq-device	: Array of FIQs to enable - should be 2 in length



Optional properties:

- st,invert-ext	: External IRQs can be inverted at will.  This property inverts

		  these IRQs using bitwise logic.  A number of defines have been

		  provided for convenience:

			ST_IRQ_SYSCFG_EXT_1_INV

			ST_IRQ_SYSCFG_EXT_2_INV

			ST_IRQ_SYSCFG_EXT_3_INV

Example:



irq-syscfg {

	compatible    = "st,stih407-irq-syscfg";

	st,syscfg     = <&syscfg_cpu>;

	st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,

			<ST_IRQ_SYSCFG_PMU_1>;

	st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,

			<ST_IRQ_SYSCFG_DISABLED>;

};

Documentation/devicetree/bindings/interrupt-controller/st,stih407-irq-syscfg.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STMicroelectronics STi System Configuration Controlled IRQs



maintainers:

  - Patrice Chotard <patrice.chotard@foss.st.com>



description:

  On STi based systems; External, CTI (Core Sight), PMU (Performance

  Management), and PL310 L2 Cache IRQs are controlled using System

  Configuration registers.  This device is used to unmask them prior to use.



properties:

  compatible:

    const: st,stih407-irq-syscfg



  st,syscfg:

    description: Phandle to Cortex-A9 IRQ system config registers

    $ref: /schemas/types.yaml#/definitions/phandle



  st,irq-device:

    description: Array of IRQs to enable.

    $ref: /schemas/types.yaml#/definitions/uint32-array

    items:

      - description: Enable the IRQ of the channel one.

      - description: Enable the IRQ of the channel two.



  st,fiq-device:

    description: Array of FIQs to enable.

    $ref: /schemas/types.yaml#/definitions/uint32-array

    items:

      - description: Enable the IRQ of the channel one.

      - description: Enable the IRQ of the channel two.



  st,invert-ext:

    description: External IRQs can be inverted at will. This property inverts

      these three IRQs using bitwise logic, each one being encoded respectively

      on the first, second and fourth bit.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 1, 2, 3, 4, 5, 6 ]



required:

  - compatible

  - st,syscfg

  - st,irq-device

  - st,fiq-device



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq-st.h>

    irq-syscfg {

        compatible    = "st,stih407-irq-syscfg";

        st,syscfg     = <&syscfg_cpu>;

        st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,

                        <ST_IRQ_SYSCFG_PMU_1>;

        st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,

                        <ST_IRQ_SYSCFG_DISABLED>;

    };

...