Commit 58ddbecb authored by Ao Zhong's avatar Ao Zhong Committed by Alex Deucher
Browse files

drm/amd/display: move remaining FPU code to dml folder 



pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
these two operations in dcn32/dcn32_resource.c still need to use FPU,
This will cause compilation to fail on ARM64 platforms because
-mgeneral-regs-only is enabled by default to disable the hardware FPU.
Therefore, imitate the dcn31_zero_pipe_dcc_fraction function in
dml/dcn31/dcn31_fpu.c, declare the dcn32_zero_pipe_dcc_fraction function
in dcn32_fpu.c, and move above two operations into this function.

Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAo Zhong <hacc1225@gmail.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64a9f19a

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+3 −2
Original line number Diff line number Diff line
@@ -1918,8 +1918,9 @@ int dcn32_populate_dml_pipes_from_context( 
		timing = &pipe->stream->timing;



		pipes[pipe_cnt].pipe.src.gpuvm = true;

		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;

		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;

		DC_FP_START();

		dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt);

		DC_FP_END();

		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;

		pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet

		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+8 −0
Original line number Diff line number Diff line
@@ -2506,3 +2506,11 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa 
	}

}



void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,

				  int pipe_cnt)

{

	dc_assert_fp_enabled();



	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;

	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;

}

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

+3 −0
Original line number Diff line number Diff line
@@ -73,4 +73,7 @@ int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, 


void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);



void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,

				  int pipe_cnt);



#endif