Commit 58caa2a5 authored by Chengchang Tang's avatar Chengchang Tang Committed by Jason Gunthorpe
Browse files

RDMA/hns: Fix timeout attr in query qp for HIP08 

On HIP08, the queried timeout attr is different from the timeout attr
configured by the user.

It is found by rdma-core testcase test_rdmacm_async_traffic:

======================================================================
FAIL: test_rdmacm_async_traffic (tests.test_rdmacm.CMTestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "./tests/test_rdmacm.py", line 33, in test_rdmacm_async_traffic
    self.two_nodes_rdmacm_traffic(CMAsyncConnection, self.rdmacm_traffic,
  File "./tests/base.py", line 382, in two_nodes_rdmacm_traffic
    raise(res)
AssertionError

Fixes: 926a01dc ("RDMA/hns: Add QP operations support for hip08 SoC")
Link: https://lore.kernel.org/r/20230512092245.344442-2-huangjunxian6@hisilicon.com


Signed-off-by: default avatarChengchang Tang <tangchengchang@huawei.com>
Signed-off-by: default avatarJunxian Huang <huangjunxian6@hisilicon.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent 866422cd

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+14 −3
Original line number Diff line number Diff line
@@ -5012,7 +5012,6 @@ static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 
static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)

{

#define QP_ACK_TIMEOUT_MAX_HIP08 20

#define QP_ACK_TIMEOUT_OFFSET 10

#define QP_ACK_TIMEOUT_MAX 31



	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
@@ -5021,7 +5020,7 @@ static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 
				   "local ACK timeout shall be 0 to 20.\n");

			return false;

		}

		*timeout += QP_ACK_TIMEOUT_OFFSET;

		*timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;

	} else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {

		if (*timeout > QP_ACK_TIMEOUT_MAX) {

			ibdev_warn(&hr_dev->ib_dev,
@@ -5307,6 +5306,18 @@ static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 
	return ret;

}



static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev,

			      struct hns_roce_v2_qp_context *context)

{

	u8 timeout;



	timeout = (u8)hr_reg_read(context, QPC_AT);

	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)

		timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;



	return timeout;

}



static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,

				int qp_attr_mask,

				struct ib_qp_init_attr *qp_init_attr)
@@ -5384,7 +5395,7 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 
	qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);



	qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);

	qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT);

	qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context);

	qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);

	qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ 
#define HNS_ROCE_V2_MAX_XRCD_NUM		0x1000000

#define HNS_ROCE_V2_RSV_XRCD_NUM		0



#define HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08    10



#define HNS_ROCE_V3_SCCC_SZ			64

#define HNS_ROCE_V3_GMV_ENTRY_SZ		32