Commit 589d9282 authored by Junhao He's avatar Junhao He Committed by Suzuki K Poulose
Browse files

coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR 



The TRCSEQRSTEVR and TRCSEQSTR registers are not implemented if the
TRCIDR5.NUMSEQSTATE == 0. Skip accessing the registers in such cases.

Fixes: 2e1cdfe1 ("coresight-etm4x: Adding CoreSight ETM4x driver")
Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230114091632.60095-1-hejunhao3@huawei.com
parent 88603b6d

drivers/hwtracing/coresight/coresight-etm4x-core.c

+12 −6
Original line number Diff line number Diff line
@@ -427,8 +427,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 
		etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);

	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));

	if (drvdata->nrseqstate) {

		etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);

		etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);

	}

	etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);

	for (i = 0; i < drvdata->nr_cntr; i++) {

		etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
@@ -1634,8 +1636,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) 
	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));



	if (drvdata->nrseqstate) {

		state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);

		state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);

	}

	state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);



	for (i = 0; i < drvdata->nr_cntr; i++) {
@@ -1763,8 +1767,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) 
	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));



	if (drvdata->nrseqstate) {

		etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);

		etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);

	}

	etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);



	for (i = 0; i < drvdata->nr_cntr; i++) {