Commit 589744db authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.14-2021-08-25' of... 

Merge tag 'amd-drm-fixes-5.14-2021-08-25' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.14-2021-08-25:

amdgpu:
- Fix for pinning display buffers multiple times
- Fix delayed work handling for GFXOFF
- Fix build when CONFIG_SUSPEND is not set

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210826032658.4068-1-alexander.deucher@amd.com
parents 4f332396 c41a4e87

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

+1 −1
Original line number Diff line number Diff line
@@ -1040,7 +1040,7 @@ void amdgpu_acpi_detect(void) 
 */

bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev)

{

#if IS_ENABLED(CONFIG_AMD_PMC) && IS_ENABLED(CONFIG_PM_SLEEP)

#if IS_ENABLED(CONFIG_AMD_PMC) && IS_ENABLED(CONFIG_SUSPEND)

	if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {

		if (adev->flags & AMD_IS_APU)

			return pm_suspend_target_state == PM_SUSPEND_TO_IDLE;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+5 −6
Original line number Diff line number Diff line
@@ -2777,13 +2777,12 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) 
	struct amdgpu_device *adev =

		container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);



	mutex_lock(&adev->gfx.gfx_off_mutex);

	if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {

	WARN_ON_ONCE(adev->gfx.gfx_off_state);

	WARN_ON_ONCE(adev->gfx.gfx_off_req_count);



	if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))

		adev->gfx.gfx_off_state = true;

}

	mutex_unlock(&adev->gfx.gfx_off_mutex);

}



/**

 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+25 −11
Original line number Diff line number Diff line
@@ -563,24 +563,38 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) 


	mutex_lock(&adev->gfx.gfx_off_mutex);



	if (!enable)

		adev->gfx.gfx_off_req_count++;

	else if (adev->gfx.gfx_off_req_count > 0)

	if (enable) {

		/* If the count is already 0, it means there's an imbalance bug somewhere.

		 * Note that the bug may be in a different caller than the one which triggers the

		 * WARN_ON_ONCE.

		 */

		if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))

			goto unlock;



		adev->gfx.gfx_off_req_count--;



	if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {

		if (adev->gfx.gfx_off_req_count == 0 && !adev->gfx.gfx_off_state)

			schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);

	} else if (!enable && adev->gfx.gfx_off_state) {

		if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {

	} else {

		if (adev->gfx.gfx_off_req_count == 0) {

			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);



			if (adev->gfx.gfx_off_state &&

			    !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {

				adev->gfx.gfx_off_state = false;



				if (adev->gfx.funcs->init_spm_golden) {

				dev_dbg(adev->dev, "GFXOFF is disabled, re-init SPM golden settings\n");

					dev_dbg(adev->dev,

						"GFXOFF is disabled, re-init SPM golden settings\n");

					amdgpu_gfx_init_spm_golden(adev);

				}

			}

		}



		adev->gfx.gfx_off_req_count++;

	}



unlock:

	mutex_unlock(&adev->gfx.gfx_off_mutex);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+5 −5
Original line number Diff line number Diff line
@@ -920,11 +920,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 
			return -EINVAL;

	}



	/* This assumes only APU display buffers are pinned with (VRAM|GTT).

	 * See function amdgpu_display_supported_domains()

	 */

	domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);



	if (bo->tbo.pin_count) {

		uint32_t mem_type = bo->tbo.resource->mem_type;

		uint32_t mem_flags = bo->tbo.resource->placement;
@@ -949,6 +944,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 
		return 0;

	}



	/* This assumes only APU display buffers are pinned with (VRAM|GTT).

	 * See function amdgpu_display_supported_domains()

	 */

	domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);



	if (bo->tbo.base.import_attach)

		dma_buf_pin(bo->tbo.base.import_attach);