Commit 5866348c authored by Xi Wang's avatar Xi Wang Committed by Zheng Zengkai
Browse files

RDMA/hns: Reorganize process of setting HEM 

mainline inclusion
from mainline-v5.13-rc1
commit c6f0411b
category: bugfix
bugzilla: 174002
CVE:NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c6f0411b960d0b5af35c78cf47cc8019bee00656

----------------------------------------------------------------------

Encapsulate configuring GMV base address and other type of HEM table into
two separate functions to make process of setting HEM clearer.

Link: https://lore.kernel.org/r/1616815294-13434-5-git-send-email-liweihang@huawei.com


Signed-off-by: default avatarXi Wang <wangxi11@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarwangsirong <wangsirong@huawei.com>
Reviewed-by: default avatarChunZhi Hu <huchunzhi@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 5a8a07b0

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+44 −33
Original line number Diff line number Diff line
@@ -1402,6 +1402,21 @@ static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 
	return ret;

}



static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,

			       dma_addr_t base_addr, u16 op)

{

	struct hns_roce_cmd_mailbox *mbox = hns_roce_alloc_cmd_mailbox(hr_dev);

	int ret;



	if (IS_ERR(mbox))

		return PTR_ERR(mbox);



	ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, obj, 0, op,

				HNS_ROCE_CMD_TIMEOUT_MSECS);

	hns_roce_free_cmd_mailbox(hr_dev, mbox);

	return ret;

}



static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)

{

	struct hns_roce_query_version *resp;
@@ -3781,12 +3796,9 @@ static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 
}



static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,

			      int step_idx)

			      int step_idx, u16 *mbox_op)

{

	int op;



	if (type == HEM_TYPE_SCCC && step_idx)

		return -EINVAL;

	u16 op;



	switch (type) {

	case HEM_TYPE_QPC:
@@ -3811,51 +3823,50 @@ static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 
		op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;

		break;

	default:

		dev_warn(hr_dev->dev,

			 "table %u not to be written by mailbox!\n", type);

		dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);

		return -EINVAL;

	}



	return op + step_idx;

	*mbox_op = op + step_idx;



	return 0;

}



static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, u64 bt_ba,

			 u32 hem_type, int step_idx)

static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,

			       dma_addr_t base_addr)

{

	struct hns_roce_cmd_mailbox *mailbox;

	struct hns_roce_cmq_desc desc;

	struct hns_roce_cfg_gmv_bt *gmv_bt =

				(struct hns_roce_cfg_gmv_bt *)desc.data;

	int ret;

	int op;

	u64 addr = to_hr_hw_page_addr(base_addr);



	if (hem_type == HEM_TYPE_GMV) {

		hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT,

					      false);

	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);



		gmv_bt->gmv_ba_l = cpu_to_le32(bt_ba >> HNS_HW_PAGE_SHIFT);

		gmv_bt->gmv_ba_h = cpu_to_le32(bt_ba >> (HNS_HW_PAGE_SHIFT +

							 32));

	gmv_bt->gmv_ba_l = cpu_to_le32(lower_32_bits(addr));

	gmv_bt->gmv_ba_h = cpu_to_le32(upper_32_bits(addr));

	gmv_bt->gmv_bt_idx = cpu_to_le32(obj /

		(HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz));



	return hns_roce_cmq_send(hr_dev, &desc, 1);

}



	op = get_op_for_set_hem(hr_dev, hem_type, step_idx);

	if (op < 0)

		return 0;



	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);

	if (IS_ERR(mailbox))

		return PTR_ERR(mailbox);

static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,

			 dma_addr_t base_addr, u32 hem_type, int step_idx)

{

	int ret;

	u16 op;



	ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,

				0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);

	if (unlikely(hem_type == HEM_TYPE_GMV))

		return config_gmv_ba_to_hw(hr_dev, obj, base_addr);



	hns_roce_free_cmd_mailbox(hr_dev, mailbox);

	if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))

		return 0;



	ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &op);

	if (ret < 0)

		return ret;



	return config_hem_ba_to_hw(hr_dev, obj, base_addr, op);

}



static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,